On Wed, Aug 07, 2019 at 08:40:58AM -0700, Paul Walmsley wrote:
> On Wed, 7 Aug 2019, Christoph Hellwig wrote:
>
> > On Wed, Aug 07, 2019 at 05:22:15PM +0200, Greg KH wrote:
> > > > Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller
> > > > driver for SiFive SoCs")
> > > > Signed-off-by: Christoph Hellwig <[email protected]>
> > > > ---
> > > > arch/riscv/mm/Makefile | 1 -
> > > > drivers/misc/Makefile | 1 +
> > > > {arch/riscv/mm => drivers/misc}/sifive_l2_cache.c | 0
> > > > 3 files changed, 1 insertion(+), 1 deletion(-)
> > > > rename {arch/riscv/mm => drivers/misc}/sifive_l2_cache.c (100%)
> > >
> > > Why isn't this in drivers/edac/ ?
> > > why is this a misc driver? Seems like it should sit next to the edac
> > > stuff.
> >
> > No idea. EDAC maintainers, would you object to taking what is
> > currently in arch/riscv/mm//sifive_l2_cache.c to drivers/edac/ ?
>
> If this driver is moved out of arch/riscv/mm, it should ideally go into
> some sort of common L2 cache controller driver directory, along
> with other L2 cache controller drivers like arch/arm/mm/*l2c*.
>
> Like many L2 cache controllers, this controller also supports cache
> flushing operations and SoC-specific way operations. We just don't use
> those on RISC-V - yet.
Well, another reason to not have it under arch/riscv/ as it is a SOC
specific driver, which we all have somewhere else, just like arm64
and new arm ports do. And especially not unconditionally built.
