On Wed, Apr 29, 2020 at 11:37:37AM +0800, ryan_chen wrote: > In AST2600 there have a slow peripheral bus between CPU > and i2c controller. > Therefore GIC i2c interrupt status clear have delay timing, > when CPU issue write clear i2c controller interrupt status. > To avoid this issue, the driver need have read after write > clear at i2c ISR. > > Signed-off-by: ryan_chen <ryan_c...@aspeedtech.com>
v0? is it a prototype?
And is there maybe a Fixes: tag for it?
> ---
> drivers/i2c/busses/i2c-aspeed.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/i2c/busses/i2c-aspeed.c b/drivers/i2c/busses/i2c-aspeed.c
> index 07c1993274c5..f51702d86a90 100644
> --- a/drivers/i2c/busses/i2c-aspeed.c
> +++ b/drivers/i2c/busses/i2c-aspeed.c
> @@ -603,6 +603,7 @@ static irqreturn_t aspeed_i2c_bus_irq(int irq, void
> *dev_id)
> /* Ack all interrupts except for Rx done */
> writel(irq_received & ~ASPEED_I2CD_INTR_RX_DONE,
> bus->base + ASPEED_I2C_INTR_STS_REG);
> + readl(bus->base + ASPEED_I2C_INTR_STS_REG);
> irq_remaining = irq_received;
>
> #if IS_ENABLED(CONFIG_I2C_SLAVE)
> @@ -645,9 +646,11 @@ static irqreturn_t aspeed_i2c_bus_irq(int irq, void
> *dev_id)
> irq_received, irq_handled);
>
> /* Ack Rx done */
> - if (irq_received & ASPEED_I2CD_INTR_RX_DONE)
> + if (irq_received & ASPEED_I2CD_INTR_RX_DONE) {
> writel(ASPEED_I2CD_INTR_RX_DONE,
> bus->base + ASPEED_I2C_INTR_STS_REG);
> + readl(bus->base + ASPEED_I2C_INTR_STS_REG);
> + }
> spin_unlock(&bus->lock);
> return irq_remaining ? IRQ_NONE : IRQ_HANDLED;
> }
> --
> 2.17.1
>
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