Add and use APIs to set the local APIC timer period instead of open coding the subtle HZ math in a all external callers, and make lapic_timer_period local to apic.c. Provide APIs to specify the frequency in both hertz and kilohertz so that Hyper-V and VMware code aren't forced to lose precision.
Opportunistically use mul_u64_u32_div() to harden against the possibility that the period in Khz is greater than 4294967, i.e. if the APIC timer runs at ~4.29 GHz. As pointed out by Sashiko, 4294968 * 1000 == 0x1_000002c0, and thus a Khz period of 4294968 would silently overflow the 32-bit unsigned integer used by most callers. Signed-off-by: Sean Christopherson <[email protected]> --- arch/x86/include/asm/apic.h | 3 ++- arch/x86/kernel/apic/apic.c | 12 +++++++++++- arch/x86/kernel/cpu/mshyperv.c | 5 +---- arch/x86/kernel/cpu/vmware.c | 4 +--- arch/x86/kernel/jailhouse.c | 2 +- arch/x86/kernel/tsc.c | 2 +- arch/x86/kernel/tsc_msr.c | 2 +- 7 files changed, 18 insertions(+), 12 deletions(-) diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h index 9cd493d467d4..cd84a94688a2 100644 --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -63,7 +63,6 @@ extern int apic_verbosity; extern int local_apic_timer_c2_ok; extern bool apic_is_disabled; -extern unsigned int lapic_timer_period; extern enum apic_intr_mode_id apic_intr_mode; enum apic_intr_mode_id { @@ -138,6 +137,8 @@ void register_lapic_address(unsigned long address); extern void setup_boot_APIC_clock(void); extern void setup_secondary_APIC_clock(void); extern void lapic_update_tsc_freq(void); +extern void apic_set_timer_period_hz(u64 period_hz, const char *source); +extern void apic_set_timer_period_khz(u64 period_khz, const char *source); #ifdef CONFIG_X86_64 static inline bool apic_force_enable(unsigned long addr) diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index aa1e19979aa8..8d3d930576fd 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -176,7 +176,7 @@ static struct resource lapic_resource = { }; /* Measured in ticks per HZ. */ -unsigned int lapic_timer_period = 0; +static unsigned int lapic_timer_period; static void apic_pm_activate(void); @@ -796,6 +796,16 @@ bool __init apic_needs_pit(void) return lapic_timer_period == 0; } +void apic_set_timer_period_khz(u64 period_khz, const char *source) +{ + lapic_timer_period = mul_u64_u32_div(period_khz, 1000, HZ); +} + +void apic_set_timer_period_hz(u64 period_hz, const char *source) +{ + lapic_timer_period = div_u64(period_hz, HZ); +} + static int __init calibrate_APIC_clock(void) { struct clock_event_device *levt = this_cpu_ptr(&lapic_events); diff --git a/arch/x86/kernel/cpu/mshyperv.c b/arch/x86/kernel/cpu/mshyperv.c index 185d4f677ec0..87beecec76f0 100644 --- a/arch/x86/kernel/cpu/mshyperv.c +++ b/arch/x86/kernel/cpu/mshyperv.c @@ -646,10 +646,7 @@ static void __init ms_hyperv_init_platform(void) u64 hv_lapic_frequency; rdmsrq(HV_X64_MSR_APIC_FREQUENCY, hv_lapic_frequency); - hv_lapic_frequency = div_u64(hv_lapic_frequency, HZ); - lapic_timer_period = hv_lapic_frequency; - pr_info("Hyper-V: LAPIC Timer Frequency: %#x\n", - lapic_timer_period); + apic_set_timer_period_hz(hv_lapic_frequency, "Hyper-V hypervisor"); } register_nmi_handler(NMI_UNKNOWN, hv_nmi_unknown, NMI_FLAG_FIRST, diff --git a/arch/x86/kernel/cpu/vmware.c b/arch/x86/kernel/cpu/vmware.c index 34b73573b108..36f779dd311d 100644 --- a/arch/x86/kernel/cpu/vmware.c +++ b/arch/x86/kernel/cpu/vmware.c @@ -424,9 +424,7 @@ static void __init vmware_platform_setup(void) #ifdef CONFIG_X86_LOCAL_APIC /* Skip lapic calibration since we know the bus frequency. */ - lapic_timer_period = ecx / HZ; - pr_info("Host bus clock speed read from hypervisor : %u Hz\n", - ecx); + apic_set_timer_period_hz(ecx, "VMware hypervisor"); #endif } else { pr_warn("Failed to get TSC freq from the hypervisor\n"); diff --git a/arch/x86/kernel/jailhouse.c b/arch/x86/kernel/jailhouse.c index f58ce9220e0f..f2d4ef89c085 100644 --- a/arch/x86/kernel/jailhouse.c +++ b/arch/x86/kernel/jailhouse.c @@ -65,7 +65,7 @@ static void jailhouse_get_wallclock(struct timespec64 *now) static void __init jailhouse_timer_init(void) { - lapic_timer_period = setup_data.v1.apic_khz * (1000 / HZ); + apic_set_timer_period_khz(setup_data.v1.apic_khz, "Jailhouse hypervisor"); } static unsigned long jailhouse_get_tsc(void) diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index ce10ae4b298b..f9ecc9256863 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -717,7 +717,7 @@ unsigned long native_calibrate_tsc(void) * lapic_timer_period here to avoid having to calibrate the APIC * timer later. */ - lapic_timer_period = crystal_khz * 1000 / HZ; + apic_set_timer_period_khz(crystal_khz, "CPUID 0x15/0x16"); #endif return crystal_khz * ebx_numerator / eax_denominator; diff --git a/arch/x86/kernel/tsc_msr.c b/arch/x86/kernel/tsc_msr.c index 48e6cc1cb017..7e990871e041 100644 --- a/arch/x86/kernel/tsc_msr.c +++ b/arch/x86/kernel/tsc_msr.c @@ -211,7 +211,7 @@ unsigned long cpu_khz_from_msr(void) pr_err("Error MSR_FSB_FREQ index %d is unknown\n", index); #ifdef CONFIG_X86_LOCAL_APIC - lapic_timer_period = (freq * 1000) / HZ; + apic_set_timer_period_khz(freq, "MSR_FSB_FREQ"); #endif /* -- 2.55.0.rc0.799.gd6f94ed593-goog
