Add stubs for the apic_set_timer_period_{,k}hz() APIs when the kernel is
built without support for a local APIC, and drop #ifdefs in callers that
don't need to check CONFIG_X86_LOCAL_APIC for other reasons.No functional change intended. Signed-off-by: Sean Christopherson <[email protected]> --- arch/x86/include/asm/apic.h | 2 ++ arch/x86/kernel/cpu/vmware.c | 2 -- arch/x86/kernel/tsc.c | 2 -- arch/x86/kernel/tsc_msr.c | 2 -- 4 files changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h index cd84a94688a2..035998555e99 100644 --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -189,6 +189,8 @@ static inline void disable_local_APIC(void) { } # define setup_boot_APIC_clock x86_init_noop # define setup_secondary_APIC_clock x86_init_noop static inline void lapic_update_tsc_freq(void) { } +static inline void apic_set_timer_period_hz(u64 period_hz, const char *source) { } +static inline void apic_set_timer_period_khz(u64 period_khz, const char *source) { } static inline void init_bsp_APIC(void) { } static inline void apic_intr_mode_select(void) { } static inline void apic_intr_mode_init(void) { } diff --git a/arch/x86/kernel/cpu/vmware.c b/arch/x86/kernel/cpu/vmware.c index 36f779dd311d..13b97265c535 100644 --- a/arch/x86/kernel/cpu/vmware.c +++ b/arch/x86/kernel/cpu/vmware.c @@ -422,10 +422,8 @@ static void __init vmware_platform_setup(void) x86_platform.calibrate_tsc = vmware_get_tsc_khz; x86_platform.calibrate_cpu = vmware_get_tsc_khz; -#ifdef CONFIG_X86_LOCAL_APIC /* Skip lapic calibration since we know the bus frequency. */ apic_set_timer_period_hz(ecx, "VMware hypervisor"); -#endif } else { pr_warn("Failed to get TSC freq from the hypervisor\n"); } diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index f9ecc9256863..4d6a446645c0 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -710,7 +710,6 @@ unsigned long native_calibrate_tsc(void) if (boot_cpu_data.x86_vfm == INTEL_ATOM_GOLDMONT) setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE); -#ifdef CONFIG_X86_LOCAL_APIC /* * The local APIC appears to be fed by the core crystal clock * (which sounds entirely sensible). We can set the global @@ -718,7 +717,6 @@ unsigned long native_calibrate_tsc(void) * timer later. */ apic_set_timer_period_khz(crystal_khz, "CPUID 0x15/0x16"); -#endif return crystal_khz * ebx_numerator / eax_denominator; } diff --git a/arch/x86/kernel/tsc_msr.c b/arch/x86/kernel/tsc_msr.c index 7e990871e041..aece062aee7e 100644 --- a/arch/x86/kernel/tsc_msr.c +++ b/arch/x86/kernel/tsc_msr.c @@ -210,9 +210,7 @@ unsigned long cpu_khz_from_msr(void) if (freq == 0) pr_err("Error MSR_FSB_FREQ index %d is unknown\n", index); -#ifdef CONFIG_X86_LOCAL_APIC apic_set_timer_period_khz(freq, "MSR_FSB_FREQ"); -#endif /* * TSC frequency determined by MSR is always considered "known" -- 2.55.0.rc0.799.gd6f94ed593-goog
