The clock (and reset) controller within the TC9564 SoC is accessed via a PCI endpoint bus through BAR 4 of the first embedded PCIe function. A syscon node is created to provide access to a range of memory that is used by the clock/reset controller and shared by other devices.
Co-developed-by: Daniel Thompson <[email protected]> Signed-off-by: Daniel Thompson <[email protected]> Signed-off-by: Alex Elder <[email protected]> --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 22 +++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index 5b7f5292a8864..a99ee153e2473 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -9,6 +9,7 @@ #define PM7250B_SID 8 #define PM7250B_SID1 9 +#include <dt-bindings/clock/toshiba,tc9564.h> #include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h> #include <dt-bindings/iio/qcom,spmi-adc7-pm7325.h> #include <dt-bindings/leds/common.h> @@ -983,7 +984,7 @@ dev@0,1 { <0x2 0x0 0x0 0x83050100 0x0 0x4000 0x0 0x80000>, <0x4 0x0 0x0 0x83050100 0x0 0x84000 0x0 0x200000>; - pci-ep-bus@4 { + pcie_s1b5d0f0_bar4_bus: pci-ep-bus@4 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -995,6 +996,25 @@ pci-ep-bus@4 { }; }; +&pcie_s1b5d0f0_bar4_bus { + syscon@0 { + compatible = "toshiba,tc9564-config", + "syscon", + "simple-mfd"; + reg = <0x0 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + tc9564_clock0: clock@1004 { + compatible = "toshiba,tc9564-clock"; + reg = <0x1004 0x10>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + }; +}; + &pm7325_gpios { kypd_vol_up_n: kypd-vol-up-n-state { pins = "gpio6"; -- 2.53.0
