Hi,
On Mon, Aug 19, 2013 at 1:16 PM, Jiri Olsa <[email protected]> wrote: > On Mon, Aug 19, 2013 at 11:16:54AM +0200, Stephane Eranian wrote: >> On Thu, Aug 15, 2013 at 3:53 PM, Andi Kleen <[email protected]> wrote: >> >> >> >> I think its a NOP; this is the global ctrl register but >> >> intel_pmu_disable_event() writes PERFEVTSELx.EN = 0, so even if you >> >> enable it in the global mask, the event should still be disabled. >> > >> > Yes the hardware ANDs the various enable bits in the different >> > registers. >> > >> Andi is correct. There is a logical AND between GLOBAL_CTRL and >> the individual PERFEVTCTL.EN bits. If the EN bit is zero, then the >> counter does not count. That also applies to fixed counters. > > right, peter mentioned I could have seen already queded > NMI comming in for that event.. > Yeah, I think you can have one NMI pending because it came while you were already servicing an NMI interrupt. Though, this is very unlikely. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
