From: Andi Kleen <[email protected]> In the PEBS handler report the transaction flags using the new generic transaction flags facility. Most of them come from the "tsx_tuning" field in PEBSv2, but the abort code is derived from the RAX register reported in the PEBS record.
v2: Fix interaction with precise-loads v3: Mask out reserved bits. More comments. v4: Adjust white space Signed-off-by: Andi Kleen <[email protected]> --- arch/x86/kernel/cpu/perf_event_intel_ds.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c b/arch/x86/kernel/cpu/perf_event_intel_ds.c index 104cbba..f798be8 100644 --- a/arch/x86/kernel/cpu/perf_event_intel_ds.c +++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c @@ -207,6 +207,8 @@ union hsw_tsx_tuning { u64 value; }; +#define PEBS_HSW_TSX_FLAGS 0xff00000000 + void init_debug_store_on_cpu(int cpu) { struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds; @@ -893,6 +895,16 @@ static void __intel_pmu_pebs_event(struct perf_event *event, (x86_pmu.intel_cap.pebs_format >= 2)) data.weight = intel_hsw_weight(pebs); + if ((event->attr.sample_type & PERF_SAMPLE_TRANSACTION) && + x86_pmu.intel_cap.pebs_format >= 2) { + data.transaction = + (pebs->tsx_tuning & PEBS_HSW_TSX_FLAGS) >> 32; + /* For RTM XABORTs also log the abort code from AX */ + if ((data.transaction & PERF_SAMPLE_TXN_TRANSACTION) && + (pebs->ax & 1)) + data.transaction |= pebs->ax & 0xff000000; + } + if (has_branch_stack(event)) data.br_stack = &cpuc->lbr_stack; -- 1.8.3.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
