On Fri, Sep 13, 2013 at 11:08:32AM -0700, Andi Kleen wrote:
> @@ -207,6 +207,8 @@ union hsw_tsx_tuning {
> u64 value;
> };
>
> +#define PEBS_HSW_TSX_FLAGS 0xff00000000
That's a 64bit value and this needs ULL.
> void init_debug_store_on_cpu(int cpu)
> {
> struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
> @@ -893,6 +895,16 @@ static void __intel_pmu_pebs_event(struct perf_event
> *event,
> (x86_pmu.intel_cap.pebs_format >= 2))
> data.weight = intel_hsw_weight(pebs);
>
> + if ((event->attr.sample_type & PERF_SAMPLE_TRANSACTION) &&
> + x86_pmu.intel_cap.pebs_format >= 2) {
> + data.transaction =
> + (pebs->tsx_tuning & PEBS_HSW_TSX_FLAGS) >> 32;
Screw checkpatch and make that an 81 char line or rename the thing
data.txn or so.
> + /* For RTM XABORTs also log the abort code from AX */
> + if ((data.transaction & PERF_SAMPLE_TXN_TRANSACTION) &&
> + (pebs->ax & 1))
> + data.transaction |= pebs->ax & 0xff000000;
Yeah, do data.txn, that also allows the above line break to go away.
> + }
> +
> if (has_branch_stack(event))
> data.br_stack = &cpuc->lbr_stack;
>
> --
> 1.8.3.1
>
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