2014-04-28 2:34 GMT+08:00 Thomas Gleixner <[email protected]>: > On Sun, 27 Apr 2014, Axel Lin wrote: > >> According to the datasheet, the attribute of Interrupt Status Register is >> RW0S, >> which means: >> Software can read the register. >> Software can also "write 1 to clear". "write 0" has no effect. >> Thus switch the read/modify/write to a simple write clear. >> >> A read/modify/write does not make sense for an irq status register like this, >> since otherwise a read/modify/write can race with a device raising an >> interrupt >> and then clear the pending bit unintentionally. > > That's right, but what you are not seeing is that this is the mask > callback which is supposed to mask the interrupt at the interrupt > controller level. > > I have a hard time to see (even without reading the data sheet) how > clearing a potentially pending interrupt in the status register will > mask the interrupt line.
ok, I'll send a v2 to update the commit log. Thanks for the review. Regards, Axel -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
