* Aravind Gopalakrishnan <aravind.gopalakrish...@amd.com> wrote:
> Newer AMD processors can generate deferred errors and can be configured
> to generate APIC interrupts on such events.
What's the wider context of this? What is it good for?
I suspect it's MCE related, but only from the diffstat:
> arch/x86/kernel/cpu/mcheck/mce.c | 1 +
> arch/x86/kernel/cpu/mcheck/mce_amd.c | 105
> ++++++++++++++++++++++++++++++-
Please provide proper high level description for the changes.
Thanks,
Ingo
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