On Fri, Sep 18, 2015 at 03:44:53PM +0200, Oleg Nesterov wrote:
> On 09/18, Peter Zijlstra wrote:
> > +static inline int atomic_read_ctrl(atomic_t *v)
> > +{
> > + int val = atomic_read(v);
> > + smp_read_barrier_depends(); /* Enforce control dependency. */
> > + return val;
> > +}
>
> Help. I am starting to think that the control dependencies is even more
> hard to understand that memory barriers...
Hehe, think of then as a load-store barrier; due to the 'impossibility'
of speculative stores (we'd see all kinds of random crap if you could
speculate stores).
> So I assume that if we have
>
> int X = 0;
> atomic_t Y = ATOMIC_INIT(0);
>
> void w(void)
> {
> X = 1;
> atomic_inc_return(&Y);
> }
>
> then
>
> void r(void)
> {
> if (atomic_read_ctrl(&Y))
> BUG_ON(X == 0);
> }
>
> should be correct? Why?
Nope, because its (again) a load-load order you have there.
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