On Mon, Feb 12, 2018 at 1:46 PM, Dave Jiang <dave.ji...@intel.com> wrote:
> Re-enable deep flush so that users always have a way to be sure that a write
> does make it all the way out to the NVDIMM. The PMEM driver writes always
> make it "all the way to the NVDIMM", and it relies on the ADR mechanism to
> flush the write buffers on power failure. Deep flush is there to explicitly
> flush those write buffers to protect against (rare) ADR failure.
> This change prevents a regression in deep flush behavior so that applications
> can continue to depend on fsync() as a mechanism to trigger deep flush in the
> filesystem-dax case.
> Fixes: 06e8ccdab15f4 ("acpi: nfit: Add support for detect platform CPU cache
> flush on power loss")
> Signed-off-by: Dave Jiang <dave.ji...@intel.com>
Thanks Dave, applied.
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