On Mon, Feb 12, 2018 at 2:53 PM, Jeff Moyer <jmo...@redhat.com> wrote:
> Dave Jiang <dave.ji...@intel.com> writes:
>
>> Re-enable deep flush so that users always have a way to be sure that a write
>> does make it all the way out to the NVDIMM. The PMEM driver writes always
>> make it "all the way to the NVDIMM", and it relies on the ADR mechanism to
>> flush the write buffers on power failure. Deep flush is there to explicitly
>> flush those write buffers to protect against (rare) ADR failure.
>> This change prevents a regression in deep flush behavior so that applications
>> can continue to depend on fsync() as a mechanism to trigger deep flush in the
>> filesystem-dax case.
>
> That's still very confusing text. Specifically, the part where you say
> that pmem driver writes always make it to the DIMM. I think the
> changelog could start with "Deep flush is there to explicitly flush
> write buffers...." Anyway, the fix looks right to me.
I ended up changing the commit message to this, let me know if it reads better:
libnvdimm: re-enable deep flush for pmem devices via fsync()
Re-enable deep flush so that users always have a way to be sure that a
write makes it all the way out to media. The PMEM driver writes always
arrive at the NVDIMM, and it relies on the ADR (Asynchronous DRAM
Refresh) mechanism to flush the write buffers on power failure. Deep
flush is there to explicitly flush those write buffers to protect
against (rare) ADR failure. This change prevents a regression in deep
flush behavior so that applications can continue to depend on fsync() as
a mechanism to trigger deep flush in the filesystem-DAX case.
Fixes: 06e8ccdab15f4 ("acpi: nfit: Add support for detect platform
CPU cache...")
Signed-off-by: Dave Jiang <dave.ji...@intel.com>
Signed-off-by: Dan Williams <dan.j.willi...@intel.com>
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