When a non-CORE DPLL is enabled via omap3_noncore_dpll_enable(), use the user's desired rate in clk->rate to determine whether to put the DPLL into bypass or lock mode, rather than reading the DPLL's current idle state from its hardware registers.
This fixes a bug observed when leaving retention. Non-CORE DPLLs were not being relocked when downstream clocks re-enabled; rather, the DPLL entered bypass mode. Problem reported by Tero Kristo <[email protected]>. linux-omap source commit is 8b1f0bd44fe490ec631230c8c040753a2bda8caa. Signed-off-by: Paul Walmsley <[email protected]> Signed-off-by: Tony Lindgren <[email protected]> Cc: Tero Kristo <[email protected]> --- arch/arm/mach-omap2/clock34xx.c | 4 +--- 1 files changed, 1 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index 844fe82..424eed6 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c @@ -280,9 +280,7 @@ static int omap3_noncore_dpll_enable(struct clk *clk) if (!dd) return -EINVAL; - rate = omap2_get_dpll_rate(clk); - - if (dd->bypass_clk->rate == rate) + if (clk->rate == dd->bypass_clk->rate) r = _omap3_noncore_dpll_bypass(clk); else r = _omap3_noncore_dpll_lock(clk); -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
