Commit 8b1f0bd44fe490ec631230c8c040753a2bda8caa introduced a bug that caused non-CORE DPLL rates to be incorrectly set on boot in omap3_noncore_dpll_enable(). Debugged by Tomi Valkeinen <[email protected]> - thanks Tomi.
Also fix omap3_noncore_dpll_set_rate() to assign clk->rate after a DPLL reprogram. Tested on 3430SDP. linux-omap source commit is 2ac1da8c787f73f067e717408e631501ba60aabc. Signed-off-by: Paul Walmsley <[email protected]> Cc: Tomi Valkeinen <[email protected]> Cc: Rick Bronson <[email protected]> Cc: Timo Kokkonen <[email protected]> Cc: Sakari Poussa <[email protected]> Signed-off-by: Tony Lindgren <[email protected]> --- arch/arm/mach-omap2/clock34xx.c | 6 ++++-- 1 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index 424eed6..c943043 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c @@ -270,7 +270,6 @@ static int _omap3_noncore_dpll_stop(struct clk *clk) static int omap3_noncore_dpll_enable(struct clk *clk) { int r; - long rate; struct dpll_data *dd; if (clk == &dpll3_ck) @@ -286,7 +285,7 @@ static int omap3_noncore_dpll_enable(struct clk *clk) r = _omap3_noncore_dpll_lock(clk); if (!r) - clk->rate = rate; + clk->rate = omap2_get_dpll_rate(clk); return r; } @@ -429,6 +428,9 @@ static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m, dd->last_rounded_n, freqsel); + if (!ret) + clk->rate = rate; + } omap3_dpll_recalc(clk); -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
