Hi Doyu-San, > > I am still going through the patch, but one quick question regarding > > this. One of the requirements of DSP memory pool is that it should > > be physically contiguous and non-cacheable. I hope the below patch > > is taking care of this requirement. > > This patch reserves a *contigious* physical memory area and passes > this physical address to the bridge driver through > ldm(platform_data). Then this area is ioremap()'ed in > "MEM_ExtPhysPoolInit()". So it should be non-cachable and contigious.
-- We validated your patch with TI's internal test suite and it looks good. The only comment I have is with this patch now we would require 2 modules to insert for DSP Bridge to work. I think it would be nice if we compile these 2 modules into 1 module so that we have only DSPBridge module. Thank you, Best regards, Hari -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
