> From: Siarhei Siamashka [mailto:siarhei.siamas...@nokia.com] > Sent: Wednesday, October 14, 2009 12:37 PM > To: ext e...@gmx.de
> What you see is just a (fake) performance boost because you have a single > physical page shared between all the virtual pages in the source buffer. So > you get no cache misses on read operations and everything seems fast. > > This is unlikely to happen on real use, and it does not reflect real memory > performance. So the benchmark is inadequate. Yep, benchmark is only useful so far. If you control factors it can be useful but it's far from 1-1, to extrapolate it to something meaningful at system level. You can actually get even 'better' numbers if you take the DDR part geometry into mind and SDRC (sdram-controller) scheduler. Our silicon validation people report out of this world numbers for very specific test cases. These are component tests for the memory controller to make sure it behaves. If you alternate between open banks you can do really fast operations. A good amount of that test is not practical to count on at HLOS level. It can help explain some anomalies and help in designing a fair test. Regards, Richard W. -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
