> Reprogramming SDRC clock to 266000000 Hz > dpll3_m2_clk rate change failed: -22 > > Why I cant't let it run only on 322 MHz?
For this I could found an answer. There is no entry for this frequency in omap_sdrc_params mt46h32m32lf6_sdrc_params (in arch/arm/mach-omap2/sdram-micron ....) -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
