This patch introduces OMAP1 DMA driver as platform device and adds support for registering through platform device layer.
Signed-off-by: Manjunatha GK <[email protected]> Cc: Benoit Cousson <[email protected]> Cc: Kevin Hilman <[email protected]> Cc: Santosh Shilimkar <[email protected]> --- arch/arm/mach-omap1/dma.c | 234 ++++++++++++++++++++++++++++++++ arch/arm/mach-omap1/include/mach/dma.h | 80 +++++++++++ 2 files changed, 314 insertions(+), 0 deletions(-) create mode 100644 arch/arm/mach-omap1/dma.c create mode 100644 arch/arm/mach-omap1/include/mach/dma.h diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c new file mode 100644 index 0000000..26ab6e3 --- /dev/null +++ b/arch/arm/mach-omap1/dma.c @@ -0,0 +1,234 @@ +/* + * dma.c - OMAP1/OMAP7xx-specific DMA code + * + * Copyright (C) 2003 - 2008 Nokia Corporation + * Author: Juha Yrjölä <[email protected]> + * DMA channel linking for 1610 by Samuel Ortiz <[email protected]> + * Graphics DMA and LCD DMA graphics tranformations + * by Imre Deak <[email protected]> + * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc. + * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc. + * + * Copyright (C) 2010 Texas Instruments, Inc. + * Converted DMA library into platform driver by Manjunatha GK <[email protected]> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/err.h> +#include <linux/slab.h> +#include <linux/pm_runtime.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/sched.h> +#include <linux/spinlock.h> +#include <linux/errno.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/device.h> + +#include <plat/dma.h> +#include <plat/tc.h> + +#define dma_read(reg) \ +({ \ + u32 __val; \ + __val = __raw_readw(dma_base + OMAP1_DMA_##reg); \ + __val; \ +}) + +#define dma_write(val, reg) \ +({ \ + __raw_writew((val), dma_base + OMAP1_DMA_##reg); \ +}) + +static struct resource res[] __initdata = { + [0] = { + .start = OMAP1_DMA_BASE, + .end = OMAP1_DMA_BASE + SZ_2K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .name = "0", + .start = INT_DMA_CH0_6, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .name = "1", + .start = INT_DMA_CH1_7, + .flags = IORESOURCE_IRQ, + }, + [3] = { + .name = "2", + .start = INT_DMA_CH2_8, + .flags = IORESOURCE_IRQ, + }, + [4] = { + .name = "3", + .start = INT_DMA_CH3, + .flags = IORESOURCE_IRQ, + }, + [5] = { + .name = "4", + .start = INT_DMA_CH4, + .flags = IORESOURCE_IRQ, + }, + [6] = { + .name = "5", + .start = INT_DMA_CH5, + .flags = IORESOURCE_IRQ, + }, + [7] = { + .name = "6", + .start = INT_DMA_LCD, + .flags = IORESOURCE_IRQ, + }, + /* irq's for omap16xx and omap7xx */ + [8] = { + .name = "7", + .start = 53 + IH2_BASE, + .flags = IORESOURCE_IRQ, + }, + [9] = { + .name = "8", + .start = 54 + IH2_BASE, + .flags = IORESOURCE_IRQ, + }, + [10] = { + .name = "9", + .start = 55 + IH2_BASE, + .flags = IORESOURCE_IRQ, + }, + [11] = { + .name = "10", + .start = 56 + IH2_BASE, + .flags = IORESOURCE_IRQ, + }, + [12] = { + .name = "11", + .start = 57 + IH2_BASE, + .flags = IORESOURCE_IRQ, + }, + [13] = { + .name = "12", + .start = 58 + IH2_BASE, + .flags = IORESOURCE_IRQ, + }, + [14] = { + .name = "13", + .start = 59 + IH2_BASE, + .flags = IORESOURCE_IRQ, + }, + [15] = { + .name = "14", + .start = 60 + IH2_BASE, + .flags = IORESOURCE_IRQ, + }, + [16] = { + .name = "15", + .start = 61 + IH2_BASE, + .flags = IORESOURCE_IRQ, + }, + [17] = { + .name = "16", + .start = 62 + IH2_BASE, + .flags = IORESOURCE_IRQ, + }, +}; + +static void __iomem *dma_base; + +static int __init omap1_system_dma_init(void) +{ + struct platform_device *pdev; + struct omap_system_dma_plat_info *pdata; + struct omap_dma_dev_attr *d; + int ret; + + pdev = platform_device_alloc("system_dma", 0); + if (!pdev) { + pr_err("%s: Unable to device alloc for dma\n", + __func__); + return -ENOMEM; + } + + ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res)); + if (ret) { + pr_err("%s: Unable to add resources for %s%d\n", + __func__, pdev->name, pdev->id); + goto exit_device_put; + } + + pdata = kzalloc(sizeof(struct omap_system_dma_plat_info), GFP_KERNEL); + if (!pdata) { + dev_err(&pdev->dev, "%s: Unable to allocate pdata for %s\n", + __func__, pdev->name); + ret = -ENOMEM; + goto exit_device_put; + } + + d = pdata->dma_attr; + + /* Valid attributes for omap1 plus processors */ + d->dev_caps = 0; + + if (cpu_is_omap15xx()) + d->dev_caps = ENABLE_1510_MODE; + + d->dev_caps |= SRC_PORT; + d->dev_caps |= DST_PORT; + d->dev_caps |= SRC_INDEX; + d->dev_caps |= DST_INDEX; + d->dev_caps |= IS_BURST_ONLY4; + d->dev_caps |= CLEAR_CSR_ON_READ; + d->dev_caps |= IS_WORD_16; + + d->lch_count = OMAP1_LOGICAL_DMA_CH_COUNT; + + if (cpu_is_omap15xx()) + d->chan_count = 9; + else if (cpu_is_omap16xx() || cpu_is_omap7xx()) { + if (!(d->dev_caps & ENABLE_1510_MODE)) + d->chan_count = 16; + else + d->chan_count = 9; + } + + pdata->omap_dma_base = (void __iomem *)res[0].start; + dma_base = pdata->omap_dma_base; + + d->dma_chan = kzalloc(sizeof(struct omap_dma_lch) * + (d->lch_count), GFP_KERNEL); + + if (!d->dma_chan) { + dev_err(&pdev->dev, "%s: Memory allcation failed" + "for dma_chan!!!\n", __func__); + goto exit_release_pdata; + } + + ret = platform_device_add_data(pdev, pdata, sizeof(*pdata)); + if (ret) { + dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n", + __func__, pdev->name, pdev->id); + goto exit_release_dma_chan; + } + ret = platform_device_add(pdev); + if (ret) { + dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n", + __func__, pdev->name, pdev->id); + goto exit_release_dma_chan; + } + +exit_release_dma_chan: + kfree(d->dma_chan); +exit_release_pdata: + kfree(pdata); +exit_device_put: + platform_device_put(pdev); + + return ret; +} +arch_initcall(omap1_system_dma_init); diff --git a/arch/arm/mach-omap1/include/mach/dma.h b/arch/arm/mach-omap1/include/mach/dma.h new file mode 100644 index 0000000..d446cdd --- /dev/null +++ b/arch/arm/mach-omap1/include/mach/dma.h @@ -0,0 +1,80 @@ +/* + * OMAP DMA controller register offsets. + * + * Copyright (C) 2003 Nokia Corporation + * Author: Juha Yrjölä <[email protected]> + * + * Copyright (C) 2010 Texas Instruments + * Converted DMA library into platform driver by Manjunatha GK <[email protected]> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_OMAP1_DMA_H +#define __ASM_ARCH_OMAP1_DMA_H +/* Hardware registers for omap1 */ +#define OMAP1_DMA_BASE (0xfffed800) + +#define OMAP1_DMA_GCR 0x400 +#define OMAP1_DMA_GSCR 0x404 +#define OMAP1_DMA_GRST 0x408 +#define OMAP1_DMA_HW_ID 0x442 +#define OMAP1_DMA_PCH2_ID 0x444 +#define OMAP1_DMA_PCH0_ID 0x446 +#define OMAP1_DMA_PCH1_ID 0x448 +#define OMAP1_DMA_PCHG_ID 0x44a +#define OMAP1_DMA_PCHD_ID 0x44c +#define OMAP1_DMA_CAPS_0_U 0x44e +#define OMAP1_DMA_CAPS_0_L 0x450 +#define OMAP1_DMA_CAPS_1_U 0x452 +#define OMAP1_DMA_CAPS_1_L 0x454 +#define OMAP1_DMA_CAPS_2 0x456 +#define OMAP1_DMA_CAPS_3 0x458 +#define OMAP1_DMA_CAPS_4 0x45a +#define OMAP1_DMA_PCH2_SR 0x460 +#define OMAP1_DMA_PCH0_SR 0x480 +#define OMAP1_DMA_PCH1_SR 0x482 +#define OMAP1_DMA_PCHD_SR 0x4c0 + +#define OMAP1_LOGICAL_DMA_CH_COUNT 17 + +/* Common channel specific registers for omap1 */ +#define OMAP1_DMA_CH_BASE(n) (0x40 * (n) + 0x00) +#define OMAP1_DMA_CSDP(n) (0x40 * (n) + 0x00) +#define OMAP1_DMA_CCR(n) (0x40 * (n) + 0x02) +#define OMAP1_DMA_CICR(n) (0x40 * (n) + 0x04) +#define OMAP1_DMA_CSR(n) (0x40 * (n) + 0x06) +#define OMAP1_DMA_CEN(n) (0x40 * (n) + 0x10) +#define OMAP1_DMA_CFN(n) (0x40 * (n) + 0x12) +#define OMAP1_DMA_CSFI(n) (0x40 * (n) + 0x14) +#define OMAP1_DMA_CSEI(n) (0x40 * (n) + 0x16) +#define OMAP1_DMA_CPC(n) (0x40 * (n) + 0x18) /* 15xx only */ +#define OMAP1_DMA_CSAC(n) (0x40 * (n) + 0x18) +#define OMAP1_DMA_CDAC(n) (0x40 * (n) + 0x1a) +#define OMAP1_DMA_CDEI(n) (0x40 * (n) + 0x1c) +#define OMAP1_DMA_CDFI(n) (0x40 * (n) + 0x1e) +#define OMAP1_DMA_CLNK_CTRL(n) (0x40 * (n) + 0x28) + +/* Channel specific registers only on omap1 */ +#define OMAP1_DMA_CSSA_L(n) (0x40 * (n) + 0x08) +#define OMAP1_DMA_CSSA_U(n) (0x40 * (n) + 0x0a) +#define OMAP1_DMA_CDSA_L(n) (0x40 * (n) + 0x0c) +#define OMAP1_DMA_CDSA_U(n) (0x40 * (n) + 0x0e) +#define OMAP1_DMA_COLOR_L(n) (0x40 * (n) + 0x20) +#define OMAP1_DMA_COLOR_U(n) (0x40 * (n) + 0x22) +#define OMAP1_DMA_CCR2(n) (0x40 * (n) + 0x24) +#define OMAP1_DMA_LCH_CTRL(n) (0x40 * (n) + 0x2a) + +#endif /* __ASM_ARCH_OMAP1_DMA_H */ -- 1.7.0.4 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
