Add a device node for the Cortex-A53 L2 cache-controller. The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as 32 KiB x 16 ways).
Signed-off-by: Geert Uytterhoeven <[email protected]> --- v3: - Remaining part of "[PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes". --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index c07f4e83b988ba42..c572527afec3403a 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -72,6 +72,12 @@ cache-level = <2>; }; + L2_CA53: cache-controller@1 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + }; + extal_clk: extal { compatible = "fixed-clock"; #clock-cells = <0>; -- 1.9.1
