On 15.02.2016 21:38, Geert Uytterhoeven wrote:
Add a device node for the Cortex-A53 L2 cache-controller.
The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as
32 KiB x 16 ways).
Signed-off-by: Geert Uytterhoeven <[email protected]>
---
v3:
- Remaining part of "[PATCH v2 6/6] arm64: renesas: r8a7795: Add L2
cache-controller nodes".
---
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index c07f4e83b988ba42..c572527afec3403a 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -72,6 +72,12 @@
cache-level = <2>;
};
+ L2_CA53: cache-controller@1 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ };
+
As we don't have any CA53 in the device tree yet, and it was rejected to
add it, I'd think that we don't want these unused entries at the moment.
I'd propose to add the CA53 entries, first. And then add their L2 cache
entries.
Based on the outcome of the discussion for the CA57 we have to see if we
want to add the unused cache-unified and cache-level, then, too.
Best regards
Dirk
