Hi Chris,
On Monday 30 Jan 2017 19:39:33 Chris Brandt wrote:
> On Monday, January 30, 2017, Laurent Pinchart wrote:
> >> + pinctrl: pinctrl@fcfe3000 {
> >> + compatible = "renesas,rza1-pinctrl";
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> +
> >> + #pinctrl-cells = <2>;
> >> +
> >> + reg = <0xfcfe3000 0xa30>, /* Pn, ..., PFCAEn */
> >> + <0xfcfe7000 0x230>, /* PIBCn, ..., PIPCn */
> >
> > What's the reason for splitting those registers in two sets ? Maybe you
> > can explain that in the DT bindings documentation that this patch series
> > is missing ;-)
>
> I left this out of my review comments, but even though the chip designers
> left a BIG HOLE in the memory map of the PFC controller, I don't think it
> will 'cost' you anything by just mapping the whole area (dead space and
> all) and getting rid of the "high and low" memory indexing thing that you
> are doing in the driver.
> There is nothing mapped in that dead area anyway.
For the first two areas, I agree. The third area is a separate pin controller
for the JTAG port, not multiplexed with the GPIO ports. I even wonder whether
it should be split in a separate DT node.
--
Regards,
Laurent Pinchart
