From: Geert Uytterhoeven <geert+rene...@glider.be>

Add a device node for the Cortex-A53 L2 cache-controller.

The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as
32 KiB x 16 ways).

Extracted from a patch by Takeshi Kihara in the BSP.

Signed-off-by: Geert Uytterhoeven <geert+rene...@glider.be>
Signed-off-by: Simon Horman <horms+rene...@verge.net.au>
---
 arch/arm64/boot/dts/renesas/r8a7796.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi 
b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index 454e1292f910..b951f5ffe9e0 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -61,6 +61,13 @@
                        cache-unified;
                        cache-level = <2>;
                };
+
+               L2_CA53: cache-controller-1 {
+                       compatible = "cache";
+                       power-domains = <&sysc R8A7796_PD_CA53_SCU>;
+                       cache-unified;
+                       cache-level = <2>;
+               };
        };
 
        extal_clk: extal {
-- 
2.7.0.rc3.207.g0ac5344

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