Hi Hans, On Fri, Dec 20, 2013 at 08:22:56PM +0100, Hans de Goede wrote: > Hi, > > On 12/20/2013 09:33 AM, Maxime Ripard wrote: > >Hi Hans, > > > >On Fri, Dec 20, 2013 at 08:29:46AM +0100, Hans de Goede wrote: > >>Hi, > >> > >>On 12/19/2013 10:49 PM, Юрий Пухальский wrote: > >>>Good UTC night! > >>> > >>> > >>>Got somewhat further, yet still there are problems. > >>>Is there anything i should change in kernel cmdline maybe? > >> > >>Is this a sun5i device, iow A10s or A13 SOC based ? If so you > >>need to build and boot with my sunxi-next u-boot branch: > >> > >>https://github.com/jwrdegoede/u-boot-sunxi/commits/sunxi-next > >> > >>The only time I've seen those clock update timeout errors is > >>on sun5i with an unfixed uboot. > > > >It would be really great if it was to work without any changes in > >u-boot. > > I agree. For this to work we need to override the initial pll6 > frequency we inherit from u-boot, which for sun5i is 2400 MHz, > which PLL6 can be configured to given its factors, but will not > actually work at. I believe this is actually a broken > power-on-reset value in PLL6-cfg, rather then u-boot's fault. > > The problem is there is no clear / clean way to fix this in > the suni-clk kernel code.
What did you think about/try ? I think that adding a new factors calculation function for sun5i's PLL6, that would limit the factors returned to whatever frequency is adequate would work. Emilio? Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com
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