Allwinner A20 SoCs have a special interrupt controller for managing NMI. Three register are present to (un)mask, control and acknowledge NMI. These two patches add a new irqchip driver in cascade with GIC.
Carlo Caione (2): ARM: sun7i: Add irqchip driver for NMI controller ARM: sun7i: dts: Add NMI irqchip support arch/arm/boot/dts/sun7i-a20.dtsi | 9 ++ drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-sun7i-nmi.c | 192 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 202 insertions(+) create mode 100644 drivers/irqchip/irq-sun7i-nmi.c -- 1.8.5.2 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/groups/opt_out.
