On 11/01/2014 15:07, Henrik Nordström wrote:
lör 2014-01-11 klockan 14:38 +0100 skrev boris brezillon:
During my reasearch regarding the HW ECC and HW randomizer of the Allwinner
NAND flash controller I found this document describing the Altera NAND
flash controller
(which is in turn based on a cadence IP):
http://www.altera.com/literature/hb/arria-v/av_54010.pdf
This really looks like the sunxi NAND flash controller (except for the
registers positions
and contents) ;-)
On a quick scan of that document I could not see very many similarities.
What parts makes you think they are similar?
1) Even if the block diagram is a bit different you find pretty much the
same
functionnalities
2) The description of how the controller works seems to match what has been
discovered by people working on the NAND driver
3) The MAP bits meaning seems to match what I experienced in my tests:
MAP bits <-> NFC_CMD_TYPE ( http://linux-sunxi.org/NFC_Register_Guide)
I'm not telling this is the exact same IP, but there is too much in
common to
tell these are totally different.
I'll do some more test to verify...
The Altera one seems to be
a much smarter controller than the Allwinner one.
Regards
Henrik
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