On 11/01/2014 17:10, boris brezillon wrote:
On 11/01/2014 17:01, Henrik Nordström wrote:
lör 2014-01-11 klockan 15:24 +0100 skrev boris brezillon:
1) Even if the block diagram is a bit different you find pretty much
the
same
functionnalities
2) The description of how the controller works seems to match what
has been
discovered by people working on the NAND driver
Does it? What I read did not feel familiar to me.
3) The MAP bits meaning seems to match what I experienced in my tests:
MAP bits <-> NFC_CMD_TYPE (
http://linux-sunxi.org/NFC_Register_Guide)
What I have seen on Allwinner:
00 = Raw command access, no magics.
I currently use this one in my driver.
01 = ECC only. Maybe can be combined with above to perform HW ECC one
sector at a time without using DMA, not sure.
This is exactly what I'm searching for.
10 = Multiple sector access with automatic ECC. Only DMA operation
possible from what I can tell. Automatically seeks and fetches ECC area
for each sector. SEQ bit controls if data & ECC is interleaved in the
page or if ECC data is all collected at the end of the page. I.e.
Adjacent or Separate Data and Spare areas.
11 = Unknown. No effect observed.
BTW, do you know where ECC bytes are stored when using HW ECC ?
1) after each sector (like what's done by the Altera IP)
2) in the spare area (or OOB area)
Okay, I found the answer to my question in your documents: it depends on
the SEQ flag in the cmd register, right ?
See notes in my nand_reg.h document for sequencing information when
using SEQ mode.
Please see
http://rhombus-tech.net/allwinner_a10/A10_register_guide/A10_NAND/ and
https://github.com/hno/Allwinner-Info/blob/master/NAND/nand_reg.h for
some more details not found in the newer wiki page.
Thanks I'll take a look.
Regards
Henrik
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