lör 2014-01-11 klockan 15:24 +0100 skrev boris brezillon: > 1) Even if the block diagram is a bit different you find pretty much the > same > functionnalities > 2) The description of how the controller works seems to match what has been > discovered by people working on the NAND driver
Does it? What I read did not feel familiar to me. > 3) The MAP bits meaning seems to match what I experienced in my tests: > MAP bits <-> NFC_CMD_TYPE ( http://linux-sunxi.org/NFC_Register_Guide) What I have seen on Allwinner: 00 = Raw command access, no magics. 01 = ECC only. Maybe can be combined with above to perform HW ECC one sector at a time without using DMA, not sure. 10 = Multiple sector access with automatic ECC. Only DMA operation possible from what I can tell. Automatically seeks and fetches ECC area for each sector. SEQ bit controls if data & ECC is interleaved in the page or if ECC data is all collected at the end of the page. I.e. Adjacent or Separate Data and Spare areas. 11 = Unknown. No effect observed. See notes in my nand_reg.h document for sequencing information when using SEQ mode. Please see http://rhombus-tech.net/allwinner_a10/A10_register_guide/A10_NAND/ and https://github.com/hno/Allwinner-Info/blob/master/NAND/nand_reg.h for some more details not found in the newer wiki page. Regards Henrik -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/groups/opt_out.
