On Mon, 2014-03-17 at 09:49 +0100, Hans de Goede wrote:
> Hi,
>
> On 03/17/2014 09:28 AM, Ian Campbell wrote:
> > On Mon, 2014-03-17 at 12:05 +0800, Chen-Yu Tsai wrote:
> >> @@ -162,40 +151,47 @@ static int mmc_clk_io_on(int sdc_no)
> >> switch (sdc_no) {
> >> case 0:
> >> /* D1-PF0, D0-PF1, CLK-PF2, CMD-PF3, D3-PF4, D4-PF5 */
> >> - writel(0x222222, &gpio_f->cfg[0]);
> >> - writel(0x555, &gpio_f->pull[0]);
> >> - writel(0xaaa, &gpio_f->drv[0]);
> >> + for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
> >> + sunxi_gpio_set_cfgpin(pin, SUNXI_GPF0_SDC0_CMD);
> >
> > I appreciate that the function is the same for each pin but this still
> > looks odd. Perhaps just #define SUNXI_GPFx_SDC0 and use that?
> >
> > I did something similar yesterday and just opencoded the calls.
> >
> >> + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
> >> + sunxi_gpio_set_drv(pin, 2);
> >
> > I was wondering about these -- do these matter even when the PIN is
> > configured for a specific function and not as a GPIO?
>
> Yes, the drive-strength and pull-up also influence the pins when
> there multiplexed to some non gpio ip-block. IE with the GMAC the
> drive-strength needs to be set according to the PHY type, for
> phys which use a DDR type signalling the drive strength must be
> 3. Likewise for DDR mmc modes (which we don't support atm, but the
> ip-block does) drive strength must be set to 3 too.
Thanks for educating me ;-)
Ian.
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