This fixes me being unable to use PLL6 as clock-source for the mmc controller. Unfortunately the DRAM controller situation is a mess. Someone will need to put a lot of time into getting DRAM going before we can do SPL on sun6i.
Signed-off-by: Hans de Goede <[email protected]> --- arch/arm/cpu/armv7/sunxi/clock_sun6i.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c index e44a460..c8886b9 100644 --- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c +++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c @@ -14,6 +14,7 @@ #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/gpio.h> +#include <asm/arch/prcm.h> #include <asm/arch/sys_proto.h> #ifdef CONFIG_SPL_BUILD @@ -21,6 +22,19 @@ void clock_init_safe(void) { struct sunxi_ccm_reg * const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + struct sunxi_prcm_reg * const prcm = + (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; + + /* Set PLL ldo voltage without this PLL6 does not work properly */ + writel(PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN | + PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140) | + PRCM_PLL_CTRL_LDO_KEY, &prcm->pll_ctrl1); + writel(PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN | + PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140) | + PRCM_PLL_CTRL_LDO_KEY, &prcm->pll_ctrl1); + writel(PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN | + PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140), + &prcm->pll_ctrl1); /* AXI and PLL1 settings from boot0 / boot1, PLL1 set to 486 Mhz */ writel(AXI_DIV_3 << AXI_DIV_SHIFT | -- 1.9.0 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
