I used gate 16 as a filler since I didn't know what to do with them.
This is my current try. It falls over when the codec clock enables. I
will fix up the DMA numbers next.
[ 14.040525] Unable to handle kernel NULL pointer dereference at
virtual address 00000036
[ 14.048633] pgd = ed3bc000
[ 14.051349] [00000036] *pgd=6d38e831, *pte=00000000, *ppte=00000000
[ 14.057517] Internal error: Oops: 17 [#1] SMP ARM
[ 14.057539] Modules linked in: sunxi_codec(+) snd_pcm_oss
snd_mixer_oss snd_pcm brcmfmac snd_timer brcmutil
[ 14.057550] CPU: 0 PID: 247 Comm: systemd-udevd Not tainted 3.15.0+ #10
[ 14.057558] task: edfccfc0 ti: ed3b6000 task.ti: ed3b6000
[ 14.057571] PC is at __clk_enable+0x14/0xa0
[ 14.057577] LR is at clk_enable+0x20/0x34
[ 14.057584] pc : [<c03e1644>] lr : [<c03e1a28>] psr: a0010093
[ 14.057584] sp : ed3b7d58 ip : 00000000 fp : bf0d9198
[ 14.057588] r10: ed1c7de4 r9 : edda0c00 r8 : bf0d9324
[ 14.057593] r7 : edda0c10 r6 : ed336780 r5 : 60010013 r4 : fffffffe
[ 14.057598] r3 : 00000000 r2 : 00000000 r1 : 009f009e r0 : fffffffe
[ 14.057604] Flags: NzCv IRQs off FIQs on Mode SVC_32 ISA ARM
Segment user
[ 14.057610] Control: 10c5387d Table: 6d3bc06a DAC: 00000015
[ 14.057615] Process systemd-udevd (pid: 247, stack limit = 0xed3b6248)
[ 14.057619] Stack: (0xed3b7d58 to 0xed3b8000)
[ 14.057626] 7d40:
00000000 fffffffe
[ 14.057635] 7d60: 60010013 c03e1a28 00000000 00000000 00000000
bf0d8524 00008000 ed3b7d84
[ 14.057646] 7d80: ecd4b800 ed3fce00 bf0d9198 edda0c10 bf0d9118
00000000 c088c470 c096cc08
[ 14.057657] 7da0: 00000016 c02fc5e4 c02fc5c4 edda0c10 bf0d9118
c02facc8 bf0d9118 edda0c10
[ 14.057667] 7dc0: ed3b7dd8 edda0c10 edda0c44 bf0d9118 00000000
00000000 ed3b6038 c02faf90
[ 14.057677] 7de0: 00000000 bf0d9118 c02faf20 c02f9130 edd0105c
edd80334 bf0d9118 ecda6800
[ 14.057688] 7e00: c0867408 c02fa2dc bf0d8dff bf0d8e00 00000073
bf0d9118 00000001 bf0db000
[ 14.057698] 7e20: ed1c7dc0 c02fb600 c02fc06c ed3b7f58 00000001
c0008870 c082f8fc 00000001
[ 14.057708] 7e40: fffffffb c0547e58 fffffffa 00000000 00000001
bf0d918c c082fe24 c0547e58
[ 14.057722] 7e60: c082e044 c0062e94 c082e044 00000000 ffffffff
c0044d18 00000000 00000001
[ 14.057732] 7e80: ed3b7f58 00000001 ed3b7f58 00000001 bf0d918c
ed1c7dc0 bf0d91d4 00000001
[ 14.057743] 7ea0: ed1c7de4 c0086254 bf0d9198 00007fff c0083780
00000000 c0083924 00000000
[ 14.057753] 7ec0: ed3b6028 bf0d9314 f0fc3588 00000000 ed3b7ee4
b6f0b8e0 f0fa1000 0002fe56
[ 14.057761] 7ee0: 00a42542 00000000 0000000e 00000000 00000000
00000000 00000000 00000000
[ 14.057770] 7f00: 00000000 00000000 00000000 00000000 00000000
00000000 00000000 00000000
[ 14.057779] 7f20: 00000000 00000000 00000180 00000000 b6f0b8e0
00000005 0000017b c000e5c4
[ 14.057789] 7f40: ed3b6000 00000000 000c4a90 c00869d0 00000002
00000000 f0fa1000 0002fe56
[ 14.057799] 7f60: f0fc2e08 f0fc2c1f f0fd0658 00002348 00002a18
00000000 00000000 00000000
[ 14.057808] 7f80: 00000030 00000031 0000001a 00000000 00000014
00000000 000c4a90 000bf110
[ 14.057818] 7fa0: 000be748 c000e420 000c4a90 000bf110 00000005
b6f0b8e0 00000000 b6f0c4ec
[ 14.057828] 7fc0: 000c4a90 000bf110 000be748 0000017b 000d48e0
00000000 00000000 000c4a90
[ 14.057838] 7fe0: beb13a70 beb13a60 b6f05697 b6e172b2 40070030
00000005 ffffffff ffffffff
[ 14.057863] [<c03e1644>] (__clk_enable) from [<c03e1a28>]
(clk_enable+0x20/0x34)
[ 14.057890] [<c03e1a28>] (clk_enable) from [<bf0d8524>]
(sunxi_codec_probe+0x184/0x3cc [sunxi_codec])
[ 14.057918] [<bf0d8524>] (sunxi_codec_probe [sunxi_codec]) from
[<c02fc5e4>] (platform_drv_probe+0x20/0x50)
[ 14.057933] [<c02fc5e4>] (platform_drv_probe) from [<c02facc8>]
(driver_probe_device+0x138/0x344)
[ 14.057945] [<c02facc8>] (driver_probe_device) from [<c02faf90>]
(__driver_attach+0x70/0x94)
[ 14.057956] [<c02faf90>] (__driver_attach) from [<c02f9130>]
(bus_for_each_dev+0x78/0x8c)
[ 14.057970] [<c02f9130>] (bus_for_each_dev) from [<c02fa2dc>]
(bus_add_driver+0x108/0x200)
[ 14.057982] [<c02fa2dc>] (bus_add_driver) from [<c02fb600>]
(driver_register+0xa4/0xe8)
[ 14.057994] [<c02fb600>] (driver_register) from [<c0008870>]
(do_one_initcall+0xc0/0x164)
[ 14.058009] [<c0008870>] (do_one_initcall) from [<c0086254>]
(load_module+0x17c0/0x1d88)
[ 14.058020] [<c0086254>] (load_module) from [<c00869d0>]
(SyS_finit_module+0x90/0xa8)
[ 14.058031] [<c00869d0>] (SyS_finit_module) from [<c000e420>]
(ret_fast_syscall+0x0/0x30)
[ 14.058042] Code: e52de004 e8bd4000 e2504000 0a000007 (e5943038)
[ 14.058050] ---[ end trace 67a1d31d9fc88bbe ]---
[ 15.085838] init: udev-fallback-graphics main process (352)
terminated with status 1
diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
index bed74a9..a347eff 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
@@ -137,6 +137,10 @@
status = "okay";
};
+ codec@1c22c00 {
+ status = "okay";
+ };
+
ir0: ir@01c21800 {
pinctrl-names = "default";
pinctrl-0 = <&ir0_pins_a>;
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 263eb79..df9690d 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -327,6 +327,30 @@
clock-output-names = "ir1";
};
+ i2s0_clk: clk@01c200b8 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200b8 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "ir1";
+ };
+
+ ac97_clk: clk@01c200bc {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200bc 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "ir1";
+ };
+
+ spdif_clk: clk@01c200c0 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200c0 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "ir1";
+ };
+
usb_clk: clk@01c200cc {
#clock-cells = <1>;
#reset-cells = <1>;
@@ -344,6 +368,30 @@
clock-output-names = "spi3";
};
+ i2s1_clk: clk@01c200d8 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200d8 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "ir1";
+ };
+
+ i2s2_clk: clk@01c200dc {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200dc 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "ir1";
+ };
+
+ codec_clk: clk@01c20140 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c20140 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "ir1";
+ };
+
mbus_clk: clk@01c2015c {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
@@ -807,6 +855,66 @@
clocks = <&osc24M>;
#pwm-cells = <3>;
};
+
+ spdif@1c21000 {
+ compatible = "allwinner,sun7i-a20-spdif";
+ reg = <0x01C21000 0x20>;
+ interrupts = <0 13 4>;
+ clocks = <&apb0_gates 1>, <&spdif_clk>;
+ dmas = <&dma 0 2>, <&dma 0 2>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ ac97@1c21400 {
+ compatible = "allwinner,sun7i-a20-ac97";
+ reg = <0x01C21400 0x20>;
+ interrupts = <0 15 4>;
+ clocks = <&apb0_gates 2>, <&ac97_clk>;
+ dmas = <&dma 0 5>, <&dma 0 5>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ i2s0: i2s@1c22000 {
+ compatible = "allwinner,sun7i-a20-i2s";
+ reg = <0x01C22000 0x20>;
+ interrupts = <0 16 4>;
+ clocks = <&apb0_gates 3>, <&i2s0_clk>;
+ dmas = <&dma 0 2>, <&dma 0 3>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ i2s1: i2s@1c22400 {
+ compatible = "allwinner,sun7i-a20-i2s";
+ reg = <0x01C22400 0x20>;
+ interrupts = <0 87 4>;
+ clocks = <&apb0_gates 4>, <&i2s1_clk>;
+ dmas = <&dma 0 4>, <&dma 0 4>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ i2s2: i2s@1c24400 {
+ compatible = "allwinner,sun7i-a20-i2s";
+ reg = <0x01C24400 0x20>;
+ interrupts = <0 90 4>;
+ clocks = <&apb0_gates 8>, <&i2s2_clk>;
+ dmas = <&dma 0 6>, <&dma 0 6>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ codec@1c22c00 {
+ compatible = "allwinner,sun7i-a20-codec";
+ reg = <0x01C22c00 0x20>;
+ interrupts = <0 30 4>;
+ clocks = <&apb0_gates 0>, <&codec_clk>;
+ dmas = <&dma 0 19>, <&dma 0 19>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
ir0: ir@01c21800 {
compatible = "allwinner,sun7i-a20-ir";
On Fri, Jun 13, 2014 at 10:26 PM, Emilio López <[email protected]> wrote:
> El 13/06/14 13:22, [email protected] escribió:
>
>> What should the clocks be?
>> Why are there three I2S devices?
>> Did I get interrupt and DMA values right?
>>
>> spdif@1c21000 {
>> compatible = "allwinner,sun7i-a20-spdif";
>> reg = <0x01C21000 0x20>;
>> interrupts = <0 13 4>;
>> clocks = <&apb1_gates 16>;
>> dmas = <&dma 0 2>, <&dma 0 2>;
>> dma-names = "rx", "tx";
>
>
> matches user manual
>
>
>> status = "disabled";
>> }
>>
>> ac97@1c21400 {
>> compatible = "allwinner,sun7i-a20-ac97";
>> reg = <0x01C21400 0x20>;
>> interrupts = <0 15 4>;
>
>
> Shouldn't this be 14? It's the next one after the SPDIF one according to the
> manual.
>
>
>> clocks = <&apb1_gates 16>;
>> dmas = <&dma 0 5>, <&dma 0 5>;
>> dma-names = "rx", "tx";
>
>
> matches user manual
>
>
>> status = "disabled";
>> }
>>
>> i2s0: i2s@1c22000 {
>> compatible = "allwinner,sun7i-a20-i2s";
>> reg = <0x01C22000 0x20>;
>> interrupts = <0 16 4>;
>> clocks = <&apb1_gates 16>;
>> dmas = <&dma 0 2>, <&dma 0 3>;
>
>
> 2 looks like a typo. 3 is IIS0 according to user manual
>
>
>> dma-names = "rx", "tx";
>> status = "disabled";
>> }
>>
>> i2s1: i2s@1c22400 {
>> compatible = "allwinner,sun7i-a20-i2s";
>> reg = <0x01C22400 0x20>;
>> interrupts = <0 87 4>;
>> clocks = <&apb1_gates 16>;
>> dmas = <&dma 0 4>, <&dma 0 4>;
>> dma-names = "rx", "tx";
>
>
> matches user manual, assuming this is IIS1
>
>
>> status = "disabled";
>> }
>>
>> i2s2: i2s@1c24400 {
>> compatible = "allwinner,sun7i-a20-i2s";
>> reg = <0x01C24400 0x20>;
>> interrupts = <0 90 4>;
>> clocks = <&apb1_gates 16>;
>> dmas = <&dma 0 6>, <&dma 0 6>;
>
>
> ditto, assuming it's IIS2
>
>
>> dma-names = "rx", "tx";
>> status = "disabled";
>> }
>>
>> codec@1c22c00 {
>> compatible = "allwinner,sun7i-a20-codec";
>> reg = <0x01C22c00 0x20>;
>> interrupts = <0 30 4>;
>> clocks = <&apb1_gates 16>;
>> dmas = <&dma 0 19>, <&dma 0 19>;
>> dma-names = "rx", "tx";
>
>
> matches
>
>> status = "disabled";
>> }
>
>
> As for the clocks, you seem to have used <&apb1_gates 16> on all, but that's
> UART0's gate according to the manual. Note that most if not all of the audio
> clocks, most importantly PLL2, AC97 and IISx clocks are not supported on our
> clock driver yet, as there were no users for them.
--
Jon Smirl
[email protected]
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