I built a spreadsheet and worked out all of the possible divider
combinations for the audio PLL2.
These two from the Allwinner code are the only two useful combinations.
/* FactorN=79, PreDiv=21, PostDiv=4,
output=24*79/21/4=22.571mhz, 44.1k series fs
FactorN=86, PreDiv=21, PostDiv=4,
output=24*86/21/4=24.571mhz, 48k series fs */
The 44.1Khz clock has a 0.0344% error.
The 48Khz clock has 0.018% error.
That's not very good accuracy for an audio clock. About 1.5 seconds
error in an hour, but that's the best you are going to get without
building external clock circuitry. Maybe the later CPUs can do better.
I'll hack together a PLL2 driver. It will be fixed to only set these
two rates. Emilio, just use it as a sample, I wouldn't want to mess up
your very pretty clock code.
--
Jon Smirl
[email protected]
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