El 13/06/14 23:55, [email protected] escribió:
So correct setting for codec clock is?codec_clk: clk@01c20140 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk";
It does not look like a mod0 to me. User manual shows just 1 bit to gate the clock, so it should just be a simple gate clock with PLL2 as parent.
reg = <0x01c20140 0x4>; clocks = <&pll2 1>; clock-output-names = "ir1"; }; And support for pll2 is missing?
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