On Tuesday, September 8, 2015 at 12:36:49 AM UTC+2, Enrico wrote:
> Il giorno lunedì 7 settembre 2015 13:04:07 UTC+2, [email protected] ha
> scritto:
> Sure! Can I paste diffs here on the list?
>
> Thanks,
>
> Rodolfo
>
> i think nobody will complain!
>
> Enrico
>
Here it is! Tomorrow I will receive a cvbs cam and I hope to have more than a
blue screen.
Rodolfo
diff -uwr sun7i_tvd/bsp_tvd.c
/A20/MarsBoard-A20-android-4.2.2-SDK-V2.0/lichee/linux-3.3/drivers/media/video/sun7i_tvd/bsp_tvd.c
--- sun7i_tvd/bsp_tvd.c 2013-03-19 19:28:41.000000000 +0100
+++
/A20/MarsBoard-A20-android-4.2.2-SDK-V2.0/lichee/linux-3.3/drivers/media/video/sun7i_tvd/bsp_tvd.c
2014-08-29 09:46:13.000000000 +0200
@@ -72,7 +72,7 @@
break;
}
REG_WR32(addr_base+0x0504,0x00000000);
- REG_WR32(addr_base+0x052c,0x00110000);
+ REG_WR32(addr_base+0x052c,0xe0110000);
//1 channel cvbs
//REG_WR32(addr_base+0x0500,0x00000111);
//REG_WR32(addr_base+0x0000,0x00000321);
@@ -98,7 +98,7 @@
break;
}
REG_WR32(addr_base+0x0504,0x00000000);
- REG_WR32(addr_base+0x052c,0x00110000);
+ REG_WR32(addr_base+0x052c,0xe0110000);
REG_WR32(addr_base+0x0500,0x00020711);
REG_WR32(addr_base+0x0000,0x00000321);
}
@@ -107,25 +107,20 @@
switch(system)
{
case TVD_NTSC://480p
- REG_WR32(addr_base+0x0008,0x00594001);
- REG_WR32(addr_base+0x0018,0x00002080);
- REG_WR32(addr_base+0x0080,0x00500082);
- REG_WR32(addr_base+0x0084,0x00610022);
-
REG_WR32(addr_base+0x0008,0x80594001);
- REG_WR32(addr_base+0x0024,0x039db10a);
- REG_WR32(addr_base+0x0028,0x000037b1);
- REG_WR32(addr_base+0x0034,0x39999999);
+ REG_WR32(addr_base+0x0034,0x20000000);
+ REG_WR32(addr_base+0x0070,0x00002050);
break;
case TVD_PAL://576p not work
- REG_WR32(addr_base+0x0008,0x10594101);
- REG_WR32(addr_base+0x0018,0x00002480);
+ REG_WR32(addr_base+0x0008,0x90594101);
+ REG_WR32(addr_base+0x0034,0x20000000);
+ REG_WR32(addr_base+0x0070,0x00002050);
REG_WR32(addr_base+0x0080,0x00500087);
REG_WR32(addr_base+0x0084,0x00c10026);
break;
}
REG_WR32(addr_base+0x0504,0x00000000);
- REG_WR32(addr_base+0x052c,0x00110000);
+ REG_WR32(addr_base+0x052c,0xe0110000);
REG_WR32(addr_base+0x0500,0x00020711);
REG_WR32(addr_base+0x0000,0x00000321);
}
diff -uwr sun7i_tvd/drv_tvd.c
/A20/MarsBoard-A20-android-4.2.2-SDK-V2.0/lichee/linux-3.3/drivers/media/video/sun7i_tvd/drv_tvd.c
--- sun7i_tvd/drv_tvd.c 2013-03-19 19:28:41.000000000 +0100
+++
/A20/MarsBoard-A20-android-4.2.2-SDK-V2.0/lichee/linux-3.3/drivers/media/video/sun7i_tvd/drv_tvd.c
2014-08-29 09:46:13.000000000 +0200
@@ -203,10 +203,14 @@
__err("get tvd clock source error!\n");
return -1;
}
- if(interface==2)
- ret = clk_set_rate(module_clk_src, 330000000);
//264000000//297000000
- else
+
+ if (interface == 2) {//YpbPr_P
+ //ret = clk_set_rate(module_clk_src, 330000000);
//264000000//297000000
+ ret = clk_set_rate(module_clk_src, 270000000);
//264000000//297000000
+ } else {//CVBS and YPbPr_I
ret = clk_set_rate(module_clk_src, 297000000);
//264000000//297000000
+ }
+
if (ret == -1)
{
__err("set tvd parent clock error!\n");
@@ -220,6 +224,25 @@
return -1;
}
+ /* add by [email protected]
+ * spec p77 TVD_CLK_REG
+ * bit[3-0] set TVD_CLK divid ratio(m)
+ * the per-divided clock is divided by(m+1). the divider is from
+ * 1 to 16
+ * 0xb,0x5 from [email protected]
+ */
+ if (interface == 2) {//YpbPr_P
+ ret = clk_set_rate(dev->module1_clk, 270000000 / 0x5);
+ } else {//CVBS and YPbPr_I
+ ret = clk_set_rate(dev->module1_clk, 297000000 / 0xb);
+ }
+
+ if (ret == -1)
+ {
+ __err("set tvd clk rate error!\n");
+ return -1;
+ }
+
if(NULL == module_clk_src || IS_ERR(module_clk_src))
{
__err("tvd module_clk_src NULL hdle\n");
@@ -968,7 +991,7 @@
break;
case TVD_PL_YUV422:
default:
- *size = dev->width * dev->height * 2;
+ *size = dev->width * dev->height * 3/2;
break;
}
--
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