From: Siarhei Siamashka <siarhei.siamas...@gmail.com>
This allows the SRAM section A2 to be exclusively used by
the OpenRISC core.
Regarding the potential U-Boot SPL size. The SRAM section A1
only has 32 KiB. But at least the stack can be set at the end
of the SRAM section B. Or runtime UCL or LZO decompression can
be used to unpack the SPL code to 0x24000-0x2FFFF and have
48 KiB of available space there.
Signed-off-by: Siarhei Siamashka <siarhei.siamas...@gmail.com>
Reviewed-by: Bernhard Nortmann <bernhard.nortm...@web.de>
---
fel.c | 17 +++++++++++++++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/fel.c b/fel.c
index 5c47189..eeed73c 100644
--- a/fel.c
+++ b/fel.c
@@ -487,6 +487,19 @@ sram_swap_buffers a10_a13_a20_sram_swap_buffers[] = {
};
/*
+ * A31 is very similar to A10/A13/A20, except that it has no SRAM at 0x8000.
+ * So we use the SRAM section B at 0x20000-0x2FFFF instead. In the FEL mode,
+ * the MMU translation table is allocated by the BROM at 0x20000. But we can
+ * also safely use it as the backup storage because the MMU is temporarily
+ * disabled during the time of the SPL execution.
+ */
+sram_swap_buffers a31_sram_swap_buffers[] = {
+ { .buf1 = 0x01800, .buf2 = 0x20000, .size = 0x800 },
+ { .buf1 = 0x05C00, .buf2 = 0x20800, .size = 0x8000 - 0x5C00 },
+ { .size = 0 } /* End of the table */
+};
+
+/*
* Use the SRAM section at 0x44000 as the backup storage. This is the memory,
* which is normally shared with the OpenRISC core (should we do an extra check
* to ensure that this core is powered off and can't interfere?).
@@ -541,8 +554,8 @@ soc_sram_info soc_sram_info_table[] = {
{
.soc_id = 0x1633, /* Allwinner A31 */
.scratch_addr = 0x1000,
- .thunk_addr = 0x46E00, .thunk_size = 0x200,
- .swap_buffers = ar100_abusing_sram_swap_buffers,
+ .thunk_addr = 0x22E00, .thunk_size = 0x200,
+ .swap_buffers = a31_sram_swap_buffers,
},
{
.soc_id = 0x1667, /* Allwinner A33 */
--
2.4.10
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