From: Siarhei Siamashka <siarhei.siamas...@gmail.com>
This allows the SRAM section A2 to be exclusively used by
the OpenRISC core.
There are no substantial differences between H3 and A10/A13/A20.
It just has 64 KiB of SRAM starting at the address 0x0 instead
of 48 KiB.
Signed-off-by: Siarhei Siamashka <siarhei.siamas...@gmail.com>
---
fel.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/fel.c b/fel.c
index eeed73c..5b3b9c3 100644
--- a/fel.c
+++ b/fel.c
@@ -574,9 +574,9 @@ soc_sram_info soc_sram_info_table[] = {
{
.soc_id = 0x1680, /* Allwinner H3 */
.scratch_addr = 0x1000,
- .mmu_tt_addr = 0x44000,
- .thunk_addr = 0x46E00, .thunk_size = 0x200,
- .swap_buffers = ar100_abusing_sram_swap_buffers,
+ .mmu_tt_addr = 0x8000,
+ .thunk_addr = 0xA200, .thunk_size = 0x200,
+ .swap_buffers = a10_a13_a20_sram_swap_buffers,
.sid_addr = 0x01C14200,
},
{
--
2.4.10
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