On Thu,  5 May 2016 20:49:49 +0200
Bernhard Nortmann <[email protected]> wrote:

Hi,

> From: Siarhei Siamashka <[email protected]>
> 
> The SCTLR bits are somewhat different because the V bit is set
> to 0 on A64 (Low exception vectors, base address 0x00000000) and
> the UNK bit (Reads of this bit return an UNKNOWN value) is also not
> the same as on the other SoCs. So the SCTLR check can be relaxed.
> 
> Tested using a custom built UART0 hello world bootable image.

I gave this a try on my Pine64. "sunxi-fel ver" detects the SoC
correctly. Also starting U-Boot (with SPL) plus writing some data (ATF
binary) somewhere into SRAM works - so I guess FEL->SPL->FEL->U-Boot
handover, SRAM access as well as the FEL stack backup work as expected.
So:

Tested-by: Andre Przywara <[email protected]>

Thanks Siarhei for coming up with this (very helpful!) and Bernhard for
pushing this.

Cheers,
Andre.

> Signed-off-by: Siarhei Siamashka <[email protected]>
> Reviewed-by: Bernhard Nortmann <[email protected]>
> ---
>  fel.c | 23 +++++++++++++++++++++--
>  1 file changed, 21 insertions(+), 2 deletions(-)
> 
> diff --git a/fel.c b/fel.c
> index 5b3b9c3..7506cf4 100644
> --- a/fel.c
> +++ b/fel.c
> @@ -258,6 +258,7 @@ void aw_fel_print_version(libusb_device_handle
> *usb) case 0x1633: soc_name="A31";break;
>       case 0x1651: soc_name="A20";break;
>       case 0x1650: soc_name="A23";break;
> +     case 0x1689: soc_name="A64";break;
>       case 0x1639: soc_name="A80";break;
>       case 0x1667: soc_name="A33";break;
>       case 0x1673: soc_name="A83T";break;
> @@ -500,6 +501,16 @@ sram_swap_buffers a31_sram_swap_buffers[] = {
>  };
>  
>  /*
> + * A64 has a large SRAM C at 0x18000, which we use as a backup
> storage
> + * for FEL stacks. As for A80, the SPL load address is 0x10000.
> + */
> +sram_swap_buffers a64_sram_swap_buffers[] = {
> +     { .buf1 = 0x11800, .buf2 = 0x18000, .size = 0x800 },
> +     { .buf1 = 0x15C00, .buf2 = 0x18800, .size = 0x8000 -
> 0x5C00 },
> +     { .size = 0 }  /* End of the table */
> +};
> +
> +/*
>   * Use the SRAM section at 0x44000 as the backup storage. This is
> the memory,
>   * which is normally shared with the OpenRISC core (should we do an
> extra check
>   * to ensure that this core is powered off and can't interfere?).
> @@ -565,6 +576,14 @@ soc_sram_info soc_sram_info_table[] = {
>               .sid_addr     = 0x01C23800,
>       },
>       {
> +             .soc_id       = 0x1689, /* Allwinner A64 */
> +             .spl_addr     = 0x10000,
> +             .scratch_addr = 0x11000,
> +             .thunk_addr   = 0x1AE00, .thunk_size = 0x200,
> +             .swap_buffers = a64_sram_swap_buffers,
> +             .sid_addr     = 0x01C14200,
> +     },
> +     {
>               .soc_id       = 0x1673, /* Allwinner A83T */
>               .scratch_addr = 0x1000,
>               .thunk_addr   = 0x46E00, .thunk_size = 0x200,
> @@ -930,9 +949,9 @@ uint32_t
> *aw_backup_and_disable_mmu(libusb_device_handle *usb,
>        * checks needs to be relaxed).
>        */
>  
> -     /* Basically, ignore M/Z/I/V bits and expect no TEX remap */
> +     /* Basically, ignore M/Z/I/V/UNK bits and expect no TEX
> remap */ sctlr = aw_get_sctlr(usb, sram_info);
> -     if ((sctlr & ~((0x7 << 11) | 1)) != 0x00C50078) {
> +     if ((sctlr & ~((0x7 << 11) | (1 << 6) | 1)) != 0x00C50038) {
>               fprintf(stderr, "Unexpected SCTLR (%08X)\n", sctlr);
>               exit(1);
>       }

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