On Wed, Jul 23, 2025 at 11:00:33AM +0100, Catalin Marinas wrote: > On Fri, Jul 18, 2025 at 11:37:37PM -0500, Jeremy Linton wrote:
> > @@ -133,17 +147,26 @@ simulate_br_blr(u32 opcode, long addr, struct pt_regs > > *regs) > > /* update pc first in case we're doing a "blr lr" */ > > instruction_pointer_set(regs, get_x_reg(regs, xn)); > > > > - /* Link register is x30 */ > > if (((opcode >> 21) & 0x3) == 1) > > - set_x_reg(regs, 30, addr + 4); > > + update_lr(regs, addr); > > } > I can see why this function was originally updating PC (in case of a blr > lr) but updating the LR was not supposed to fail. With GCS, I think we > should follow similar logic to simulate_b_bl() and skip updating PC/LR > if the write to the GCS failed (assuming that's what the hardware does, > I haven't checked the spec). Yes, the pseudocode does the GCS validation before it starts updating BTYPE or any of the registers.
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