I don't see how these patches work. (I may be confused - I've not had
any coffee yet :-)
- The hcca is allocated from consistent memory but then bus_to_virt is
used on the allocation (which will fail, at least on some
implementations).
- I think there is more than one place where the cache needs to be
invalidated or written back to guarantee the transfered data
- if the data needs to be flushed/invalidated, why don't the td's &
ed's? with just these patches won't the td's & ed's will come from
cached memory?
Did I miss something?
(I'm not going to hold the strong-arm ohci driver up as a pretty solution,
but it I beleive it gets close to solving all these problems and has
flush/invalidate macros in the right places)
-brad
David Brownell wrote:
>This is a multi-part message in MIME format.
>
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>These two patches basically come from Steve Longerbeam
>(MontaVista) and are part of what's needed to make OHCI
>work on MIPS and other platforms (ARM, ...) that
>
> - ohci-hcca.patch ... makes one of the types of memory
> shared between host and HC use "pci consistent" memory.
>
> - ochi-wback.patch ... fix a caching problem on MIPS
>
>The HCCA patch looks big, but it's mostly changing from
>member to pointer access. Some more patches are needed
>to make OHCI work on platforms that need "consistent"
>DMA magic, but I'd like to see this part integrated first.
>
>- Dave
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