David Brownell wrote:
> Hi Brad,
>
> > - The hcca is allocated from consistent memory but then bus_to_virt is
> > used on the allocation (which will fail, at least on some
> > implementations).
>
> That is, in hc_start() about line 2033? It should use ohci->hcca_dma,
> not virt_to_bus(ohci->hcca), yes. Good catch! I'll send out an
> updated ohci-hcca.patch soon.
>
> Was that the only real difference between the hcca deltas in your ARM
> version and in this patch? It ought to be.
>
> > - I think there is more than one place where the cache needs to be
> > invalidated or written back to guarantee the transfered data
>
> Actually, maybe it's better to hold off on that ohci-wback patch.
> The data buffer should really be getting the pci_map_single()
> treatment.
Hi Dave and Brad,
You're referring to the TD data buffer, right? On the MIPS board
I was testing with (based on a QED RM5231), it was only necessary
to wback-invalidate the buffer in one place: just before linking the
TD onto the ED chain. So I think for performance arguments, it would
be better to leave it as a cacheable data buffer, and then just write it
back to memory just once - just before submitting it to the controller.
As for the number of places where the cache needs to be written back/inv,
with my patch the above was the only place required, because the EDs, TDs,
and HCCA were all allocated with pci_consistent, so the only remaining
controller-aware buffer that was cacheable was the TDs data buffer.
Steve
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