David.B> The reason I keep ending up thinking that readl-elimination David.B> must be OK (me agreeing with Martin) is that the memory David.B> there came from dma_alloc_coherent() ... so if anything's David.B> wrong, it'd be at most lack of rmb(), not a stale-cache David.B> kind of thing.
It's not an issue of DMA coherency, it's an issue of DMA vs. interrupt ordering. I believe the WHD interrupt is arriving at the CPU before
Which is what I sketched to Martin, as the reason to be interested in a patch that was equivalent to your second patch.
Unfortunately that doesn't check out as being "the" fix here. Martin still saw the problem. (And I don't see how it'd be what gave me several hard lockups ... but it didn't work either, and the day before, without that change, no lockup.)
the DMA update to the HCCA is done. In my second patch, the readl() at the beginning of the interrupt ensures that the DMA update to the HCCA is completed before the readl() returns data.
DMA-coherent memory is defined as "memory for which a write by either the device or the processor can immediately be read by the processor or device without having to worry about caching effects." Such a write-buffering mechanism is clearly a type of (write-)caching effect, and readl() would be a kind of dma_rmb(), if you will. I suspect the docs are wrong about what dma-coherent means.
If this is correct, then the first patch is probably a better approach:
... - ed->tick = OHCI_FRAME_NO(ohci->hcca) + 1; + ed->tick = OHCI_FRAME_NO(ohci->hcca) + 2; ..
This actually makes tons of sense if you think of it like jiffies: you
need to make sure you delay at least one full frame-interval.
Right, I had that theory too. As I reported, it doesn't check out as the only issue. Plus, even assuming it's correct, adding another millisecond slows down some common operations even more. I'd rather just slow down just the "right" paths, rather than all of them ... :)
- Dave
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