>>>>> On Sun, 7 Mar 2004 22:18:02 -0800, Grant Grundler <[EMAIL PROTECTED]> said:
>> `Such a write-buffering mechanism is clearly a type of
>> (write-)caching effect,
Grant> No - the data is still in flight and in some deterministic
Grant> time frame will become visible to the CPU. Calling it a
Grant> "caching effect" confuses the issues even worse.
That's why I'm so unhappy that the PCI interface used the term
"consistent" memory, when it should have said "coherent". We
should nail a plate on everbody's forehead saying:
consistency = coherency + ordering
Perhaps then people would start to have a clear distincition between
the meaning of the two terms (or at least it would force them to think
about it! ;-).
But in any case, as later experimentation confirmed, the USB bug isn't
(just) an ordering issue. The order of operation described in the
OHCI spec does not rely on any specific order of interrupt delivery at
all, so I was wrong about that.
--david
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