On Mon, 14 Jun 2004, Alan Cox wrote: > On Llu, 2004-06-14 at 17:11, Alan Stern wrote: > > The computers you mentioned use PPC processors. Do you know if these > > cache-line effects are equally important for Intel x86 machines? > > x86 systems are supposed to be cache coherent in this situation. The > bridge will untangle the mess as neccessary. The PC is the unusual one > here - most other platforms (eg mips) behave like the PPC
Okay. So we do need to put the parts written by the hardware and the parts used by the software on different cache lines for non-PC platforms. Is there an easy way to do this without also paying the alignment penalty on platforms that don't require it (or even just on x86)? Or should we simply accept the wasted space? Alan Stern ------------------------------------------------------- This SF.Net email is sponsored by The 2004 JavaOne(SM) Conference Learn from the experts at JavaOne(SM), Sun's Worldwide Java Developer Conference, June 28 - July 1 at the Moscone Center in San Francisco, CA REGISTER AND SAVE! http://java.sun.com/javaone/sf Priority Code NWMGYKND _______________________________________________ [EMAIL PROTECTED] To unsubscribe, use the last form field at: https://lists.sourceforge.net/lists/listinfo/linux-usb-devel
