Alan Cox wrote:
On Llu, 2004-06-14 at 17:11, Alan Stern wrote:
The computers you mentioned use PPC processors. Do you know if these
cache-line effects are equally important for Intel x86 machines?
x86 systems are supposed to be cache coherent in this situation. The
bridge will untangle the mess as neccessary. The PC is the unusual one
here - most other platforms (eg mips) behave like the PPC
Seems like the dma_alloc_coherent() API spec can't be
implemented on such machines then, since it's defined
to return memory(*) such that:
... a write by either the device or the processor
can immediately be read by the processor or device
without having to worry about caching effects.
Seems like the documentation should change to explain
under what circumstances "coherent" memory will exhibit
cache-incoherent behavior, and how to cope with that.
(Then lots of drivers would need to change.)
OR ... maybe the bug is just that those PPC processors
can't/shouldn't claim to implement that API. At which
point all drivers relying on that API (including all
the USB HCDs and many of the USB drivers) stop working.
- Dave
(*) DMA-API.txt uses two terms for this: "coherent" and "consistent".
DMA-mapping.txt only uses "consistent".
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