> > x86 systems are supposed to be cache coherent in this situation. The > > bridge will untangle the mess as neccessary. The PC is the unusual one > > here - most other platforms (eg mips) behave like the PPC > > Okay. So we do need to put the parts written by the hardware and the > parts used by the software on different cache lines for non-PC platforms.
I always wondered about transfer buffers... does kmalloc hand out memory in cache line aligned pieces? Is it possible for different kmalloc'd chunks of memory to live in the same cache line? Ciao, Duncan. ------------------------------------------------------- This SF.Net email is sponsored by The 2004 JavaOne(SM) Conference Learn from the experts at JavaOne(SM), Sun's Worldwide Java Developer Conference, June 28 - July 1 at the Moscone Center in San Francisco, CA REGISTER AND SAVE! http://java.sun.com/javaone/sf Priority Code NWMGYKND _______________________________________________ [EMAIL PROTECTED] To unsubscribe, use the last form field at: https://lists.sourceforge.net/lists/listinfo/linux-usb-devel
