Hello LinuxBios elders,
I'm sorry to bother you.
I'm begining to study LinuxBios and I have some problem in it.
Hope you can give me some idea.
My target board is an AMD Opteron (chipset: K8 / 8111 / 8131) mainboard,
it is similar to Tyan s2880 / s2881 / s2882.
So I base on Tyan s2880 to change some config file to compile a linuxbios.rom,
but it doesn't work.
Following is what do I changed in s2880:
1. I changed the payload path in targets/tyan/s2880/Config.lb.
2. modify src/mainboard/tyan/s2880/Config.lb as 42812-pci.txt. ( as attachment )
I don't know is it correct that I modified. If you have interest you can refer to Attachment.
3. generated irq_tables.c by getpir.c and replaced the original one.
compile and burn it in rom.
After I boot up the target board, it always alert emergency beep.
Then, I unmark some debug message in 'src/northbridge/amd/amdk8/raminit.c' to see where is it hang.
The last step is hang on setup_default_resource_map() in 'src/mainboard/tyan/s2880/cache_as_ram_auto.c',
I can see it from serial console ( as attachment again. )
Is there any configuration I should change, and I didn't do ?
How can I debug it ?
Thanks a lot.
--
Best Regards,
Vincente Tsou
Engineer
R/D, S/W Dept.
NEXCOM International Co.
Tel: 886-2-82280606 Ext. 3205
Fax: 886-2-82280506
E-mail: [EMAIL PROTECTED]
Web: http://www.nexcom.com.tw/
##
## Compute the location and size of where this firmware image
## (linuxBIOS plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
else
default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
default ROM_SECTION_OFFSET = 0
end
##
## Compute the start location and size size of
## The linuxBIOS bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET +
1)
##
## Compute where this copy of linuxBIOS will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
##
## Compute a range of ROM that can cached to speed up linuxBIOS,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
##
default XIP_ROM_SIZE=65536
default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
arch i386 end
##
## Build the objects we have code for in this directory.
##
driver mainboard.o
#dir /drivers/si/3114
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
if USE_DCACHE_RAM
if CONFIG_USE_INIT
makerule ./auto.o
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS)
$(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c
-o auto.o"
end
else
makerule ./auto.inc
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS)
$(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c
-S -o $@"
action "perl -e 's/.rodata/.rom.data/g' -pi $@"
action "perl -e 's/.text/.section .rom.text/g' -pi $@"
end
end
else
##
## Romcc output
##
makerule ./failover.E
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I.
$(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./failover.inc
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -O --label-prefix=failover -I$(TOP)/src -I.
$(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./auto.E
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS)
$(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS)
$(MAINBOARD)/auto.c -o $@"
end
end
##
## Build our 16 bit and 32 bit linuxBIOS entry code
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
ldscript /cpu/x86/16bit/entry16.lds
end
mainboardinit cpu/x86/32bit/entry32.inc
if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds
end
end
##
## Build our reset vector (This is where linuxBIOS is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
mainboardinit cpu/x86/32bit/reset32.inc
ldscript /cpu/x86/32bit/reset32.lds
end
if USE_DCACHE_RAM
else
### Should this be in the northbridge code?
mainboardinit arch/i386/lib/cpu_reset.inc
end
##
## Include an id string (For safe flashing)
##
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
if USE_DCACHE_RAM
##
## Setup Cache-As-Ram
##
mainboardinit cpu/amd/car/cache_as_ram.inc
end
###
### This is the early phase of linuxBIOS startup
### Things are delicate and we test to see if we should
### failover to another image.
###
if USE_FALLBACK_IMAGE
if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover.lds
else
ldscript /arch/i386/lib/failover.lds
mainboardinit ./failover.inc
end
end
###
### O.k. We aren't just an intermediary anymore!
###
##
## Setup RAM
##
if USE_DCACHE_RAM
if CONFIG_USE_INIT
initobject auto.o
else
mainboardinit ./auto.inc
end
else
##
## Setup RAM
##
mainboardinit cpu/x86/fpu/enable_fpu.inc
mainboardinit cpu/x86/mmx/enable_mmx.inc
mainboardinit cpu/x86/sse/enable_sse.inc
mainboardinit ./auto.inc
mainboardinit cpu/x86/sse/disable_sse.inc
mainboardinit cpu/x86/mmx/disable_mmx.inc
end
##
## Include the secondary Configuration files
##
if CONFIG_CHIP_NAME
config chip.h
end
# sample config for tyan/s2880
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on
chip cpu/amd/socket_940
device apic 0 on end
end
end
device pci_domain 0 on
chip northbridge/amd/amdk8
device pci 18.0 on end # LDT0
device pci 18.0 on end # LDT1
device pci 18.0 on # northbridge
# devices on link 0, link 0 == LDT 0
chip southbridge/amd/amd8131
# the on/off keyword is mandatory
device pci 8.0 on
chip drivers/pci/onboard
device pci 4.0 on end
#broadcom
device pci 4.1 on end
end
end
device pci 8.1 on end
device pci 9.0 on end
device pci 9.1 on end
end
chip southbridge/amd/amd8111
# this "device pci 0.0" is the parent
the next one
# PCI bridge
device pci 6.0 on
device pci 6.0 on end
device pci 6.1 on end
device pci 6.2 off end
device pci 7.0 off end
chip drivers/pci/onboard
#device pci 5.0 on end
#some sata
device pci 0.0 on end
# AMD-8111 USB
device pci 0.1 on end
# AMD-8111 USB
device pci 2.0 on end
# ATI Rage XL
device pci 4.0 on end
# Intel Ethernet Pro 100
end
#chip drivers/pci/onboard
# device pci 6.0 on end
#adti
# register "rom_address"
= "0xfff80000"
#end
end
# ISA bridge
device pci 7.0 on
chip superio/winbond/w83627hf
device pnp 2e.0 on #
Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.1 off #
Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 2e.2 on #
Com1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 off #
Com2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.5 on #
Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
end
device pnp 2e.6 off #
CIR
io 0x60 = 0x100
end
device pnp 2e.7 off #
GAME_MIDI_GIPO1
io 0x60 = 0x220
io 0x62 = 0x300
irq 0x70 = 9
end
device pnp 2e.8 off end
# GPIO2
device pnp 2e.9 off end
# GPIO3
device pnp 2e.a off end
# ACPI
device pnp 2e.b on #
HW Monitor
io 0x60 = 0x290
irq 0x70 = 5
end
end
end
device pci 7.1 on end # AMD-8111 IDE
device pci 7.2 on end # AMD-8111
SMBus 2.0
device pci 7.3 on end # AMD-8111 ACPI
device pci 7.5 off end
device pci 7.6 off end
register "ide0_enable" = "1"
register "ide1_enable" = "1"
end
end # device pci 18.0
device pci 18.0 on end #K8 HyperTransport Technology
Configuration
device pci 18.0 on end #K8 HyperTransport Technology
Configuration
device pci 18.1 on end #K8 Address Map
device pci 18.2 on end #K8 DRAM Controller
device pci 18.3 on end #K8 Miscellaneous Control
end
end
end
00:06.0 PCI bridge: Advanced Micro Devices [AMD] AMD-8111 PCI (rev 07)
00:07.0 ISA bridge: Advanced Micro Devices [AMD] AMD-8111 LPC (rev 05)
00:07.1 IDE interface: Advanced Micro Devices [AMD] AMD-8111 IDE (rev 03)
00:07.2 SMBus: Advanced Micro Devices [AMD] AMD-8111 SMBus 2.0 (rev 02)
00:07.3 Bridge: Advanced Micro Devices [AMD] AMD-8111 ACPI (rev 05)
00:08.0 PCI bridge: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge (rev 12)
00:08.1 PIC: Advanced Micro Devices [AMD] AMD-8131 PCI-X APIC (rev 01)
00:09.0 PCI bridge: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge (rev 12)
00:09.1 PIC: Advanced Micro Devices [AMD] AMD-8131 PCI-X APIC (rev 01)
00:18.0 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron]
HyperTransport Technology Configuration
00:18.1 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address
Map
00:18.2 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM
Controller
00:18.3 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron]
Miscellaneous Control
01:00.0 USB Controller: Advanced Micro Devices [AMD] AMD-8111 USB (rev 0b)
01:00.1 USB Controller: Advanced Micro Devices [AMD] AMD-8111 USB (rev 0b)
01:02.0 VGA compatible controller: ATI Technologies Inc Rage XL (rev 27)
01:04.0 Ethernet controller: Intel Corp. 82557/8/9 [Ethernet Pro 100] (rev 10)
03:04.0 Ethernet controller: Broadcom Corporation NetXtreme BCM5704S Gigabit
Ethernet (rev 03)
03:04.1 Ethernet controller: Broadcom Corporation NetXtreme BCM5704S Gigabit
Ethernet (rev 03)
00:06.0 Class 0604: 1022:7460 (rev 07)
00:07.0 Class 0601: 1022:7468 (rev 05)
00:07.1 Class 0101: 1022:7469 (rev 03)
00:07.2 Class 0c05: 1022:746a (rev 02)
00:07.3 Class 0680: 1022:746b (rev 05)
00:08.0 Class 0604: 1022:7450 (rev 12)
00:08.1 Class 0800: 1022:7451 (rev 01)
00:09.0 Class 0604: 1022:7450 (rev 12)
00:09.1 Class 0800: 1022:7451 (rev 01)
00:18.0 Class 0600: 1022:1100
00:18.1 Class 0600: 1022:1101
00:18.2 Class 0600: 1022:1102
00:18.3 Class 0600: 1022:1103
01:00.0 Class 0c03: 1022:7464 (rev 0b)
01:00.1 Class 0c03: 1022:7464 (rev 0b)
01:02.0 Class 0300: 1002:4752 (rev 27)
01:04.0 Class 0200: 8086:1229 (rev 10)
03:04.0 Class 0200: 14e4:16a8 (rev 03)
03:04.1 Class 0200: 14e4:16a8 (rev 03)
00:06.0 PCI bridge: Advanced Micro Devices [AMD] AMD-8111 PCI (rev 07) (prog-if
00 [Normal decode])
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr-
Stepping- SERR+ FastB2B-
Status: Cap+ 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
Latency: 64
Bus: primary=00, secondary=01, subordinate=01, sec-latency=64
I/O behind bridge: 00009000-0000bfff
Memory behind bridge: fc900000-fe9fffff
Prefetchable memory behind bridge: fff00000-000fffff
Secondary status: 66Mhz- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort+ <SERR- <PERR-
BridgeCtl: Parity+ SERR+ NoISA- VGA+ MAbort- >Reset- FastB2B-
Capabilities: [c0] HyperTransport: Slave or Primary Interface
!!! Possibly incomplete decoding
Command: BaseUnitID=6 UnitCnt=4 MastHost- DefDir-
Link Control 0: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO-
<CRCErr=0
Link Config 0: MLWI=8bit MLWO=8bit LWI=8bit LWO=8bit
Link Control 1: CFlE- CST- CFE- <LkFail+ Init- EOC+ TXO+
<CRCErr=0
Link Config 1: MLWI=8bit MLWO=8bit LWI=8bit LWO=8bit
Revision ID: 1.02
Capabilities: [f0] HyperTransport: Interrupt Discovery and Configuration
00:07.0 ISA bridge: Advanced Micro Devices [AMD] AMD-8111 LPC (rev 05)
Subsystem: Advanced Micro Devices [AMD] AMD-8111 LPC
Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
Status: Cap- 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
Latency: 0
00:07.1 IDE interface: Advanced Micro Devices [AMD] AMD-8111 IDE (rev 03)
(prog-if 8a [Master SecP PriP])
Subsystem: Advanced Micro Devices [AMD] AMD-8111 IDE
Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
Latency: 32
Region 4: I/O ports at ffa0 [size=16]
00:07.2 SMBus: Advanced Micro Devices [AMD] AMD-8111 SMBus 2.0 (rev 02)
Subsystem: Advanced Micro Devices [AMD] AMD-8111 SMBus 2.0
Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
Interrupt: pin D routed to IRQ 11
Region 0: I/O ports at cc00 [size=32]
00:07.3 Bridge: Advanced Micro Devices [AMD] AMD-8111 ACPI (rev 05)
Subsystem: Advanced Micro Devices [AMD] AMD-8111 ACPI
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
00:08.0 PCI bridge: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge (rev 12)
(prog-if 00 [Normal decode])
Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr-
Stepping- SERR+ FastB2B-
Status: Cap+ 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
Latency: 64
Bus: primary=00, secondary=02, subordinate=02, sec-latency=64
I/O behind bridge: 0000f000-00000fff
Memory behind bridge: fff00000-000fffff
Prefetchable memory behind bridge: 00000000fff00000-0000000000000000
Secondary status: 66Mhz+ FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort+ <SERR- <PERR-
BridgeCtl: Parity+ SERR+ NoISA+ VGA- MAbort- >Reset- FastB2B-
Capabilities: [a0] PCI-X bridge device.
Secondary Status: 64bit+, 133MHz+, SCD-, USC-, SCO-, SRD- Freq=3
Status: Bus=0 Dev=8 Func=0 64bit+ 133MHz+ SCD- USC-, SCO-, SRD-
: Upstream: Capacity=14, Commitment Limit=65535
: Downstream: Capacity=2, Commitment Limit=65535
Capabilities: [b8] HyperTransport: Interrupt Discovery and Configuration
Capabilities: [c0] HyperTransport: Slave or Primary Interface
!!! Possibly incomplete decoding
Command: BaseUnitID=8 UnitCnt=2 MastHost- DefDir-
Link Control 0: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO-
<CRCErr=0
Link Config 0: MLWI=16bit MLWO=16bit LWI=8bit LWO=8bit
Link Control 1: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO-
<CRCErr=0
Link Config 1: MLWI=8bit MLWO=8bit LWI=8bit LWO=8bit
Revision ID: 1.02
00:08.1 PIC: Advanced Micro Devices [AMD] AMD-8131 PCI-X APIC (rev 01) (prog-if
10 [IO-APIC])
Subsystem: Advanced Micro Devices [AMD] AMD-8131 PCI-X APIC
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
Latency: 0
Region 0: Memory at febff000 (64-bit, non-prefetchable) [size=4K]
00:09.0 PCI bridge: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge (rev 12)
(prog-if 00 [Normal decode])
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr-
Stepping- SERR+ FastB2B-
Status: Cap+ 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
Latency: 64
Bus: primary=00, secondary=03, subordinate=03, sec-latency=64
I/O behind bridge: 0000f000-00000fff
Memory behind bridge: fea00000-feafffff
Prefetchable memory behind bridge: 00000000fff00000-0000000000000000
Secondary status: 66Mhz+ FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort+ <SERR- <PERR-
BridgeCtl: Parity+ SERR+ NoISA+ VGA- MAbort- >Reset- FastB2B-
Capabilities: [a0] PCI-X bridge device.
Secondary Status: 64bit+, 133MHz+, SCD-, USC-, SCO-, SRD- Freq=3
Status: Bus=0 Dev=9 Func=0 64bit+ 133MHz+ SCD- USC-, SCO-, SRD-
: Upstream: Capacity=14, Commitment Limit=65535
: Downstream: Capacity=2, Commitment Limit=65535
Capabilities: [b8] HyperTransport: Interrupt Discovery and Configuration
00:09.1 PIC: Advanced Micro Devices [AMD] AMD-8131 PCI-X APIC (rev 01) (prog-if
10 [IO-APIC])
Subsystem: Advanced Micro Devices [AMD] AMD-8131 PCI-X APIC
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
Latency: 0
Region 0: Memory at febfe000 (64-bit, non-prefetchable) [size=4K]
00:18.0 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron]
HyperTransport Technology Configuration
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort-
<MAbort- >SERR- <PERR-
Capabilities: [80] HyperTransport: Host or Secondary Interface
!!! Possibly incomplete decoding
Command: WarmRst+ DblEnd-
Link Control: CFlE- CST- CFE- <LkFail+ Init- EOC+ TXO+ <CRCErr=0
Link Config: MLWI=16bit MLWO=16bit LWI=N/C LWO=N/C
Revision ID: 1.02
Capabilities: [a0] HyperTransport: Host or Secondary Interface
!!! Possibly incomplete decoding
Command: WarmRst+ DblEnd-
Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0
Link Config: MLWI=16bit MLWO=16bit LWI=8bit LWO=8bit
Revision ID: 1.02
Capabilities: [c0] HyperTransport: Host or Secondary Interface
!!! Possibly incomplete decoding
Command: WarmRst+ DblEnd-
Link Control: CFlE- CST- CFE- <LkFail+ Init- EOC+ TXO+ <CRCErr=0
Link Config: MLWI=16bit MLWO=16bit LWI=N/C LWO=N/C
Revision ID: 1.02
00:18.1 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address
Map
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort-
<MAbort- >SERR- <PERR-
00:18.2 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM
Controller
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort-
<MAbort- >SERR- <PERR-
00:18.3 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron]
Miscellaneous Control
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort-
<MAbort- >SERR- <PERR-
01:00.0 USB Controller: Advanced Micro Devices [AMD] AMD-8111 USB (rev 0b)
(prog-if 10 [OHCI])
Subsystem: Advanced Micro Devices [AMD] AMD-8111 USB
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr-
Stepping- SERR+ FastB2B-
Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
Latency: 64 (20000ns max)
Interrupt: pin D routed to IRQ 11
Region 0: Memory at fe9fd000 (32-bit, non-prefetchable) [size=4K]
01:00.1 USB Controller: Advanced Micro Devices [AMD] AMD-8111 USB (rev 0b)
(prog-if 10 [OHCI])
Subsystem: Advanced Micro Devices [AMD] AMD-8111 USB
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr-
Stepping- SERR+ FastB2B-
Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
Latency: 64 (20000ns max)
Interrupt: pin D routed to IRQ 11
Region 0: Memory at fe9fe000 (32-bit, non-prefetchable) [size=4K]
01:02.0 VGA compatible controller: ATI Technologies Inc Rage XL (rev 27)
(prog-if 00 [VGA])
Subsystem: ATI Technologies Inc Rage XL
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping+ SERR- FastB2B-
Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
Latency: 64 (2000ns min), Cache Line Size 10
Interrupt: pin A routed to IRQ 10
Region 0: Memory at fd000000 (32-bit, non-prefetchable) [size=16M]
Region 1: I/O ports at b000 [size=256]
Region 2: Memory at fe9ff000 (32-bit, non-prefetchable) [size=4K]
Expansion ROM at fe9c0000 [disabled] [size=128K]
Capabilities: [5c] Power Management version 2
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA
PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
01:04.0 Ethernet controller: Intel Corp. 82557/8/9 [Ethernet Pro 100] (rev 10)
Subsystem: Intel Corp.: Unknown device 0070
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr-
Stepping- SERR+ FastB2B-
Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
Latency: 64 (2000ns min, 14000ns max), Cache Line Size 10
Interrupt: pin A routed to IRQ 9
Region 0: Memory at fe9fc000 (32-bit, non-prefetchable) [size=4K]
Region 1: I/O ports at bc00 [size=64]
Region 2: Memory at fe9a0000 (32-bit, non-prefetchable) [size=128K]
Expansion ROM at fe9e0000 [disabled] [size=64K]
Capabilities: [dc] Power Management version 2
Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA
PME(D0+,D1+,D2+,D3hot+,D3cold+)
Status: D0 PME-Enable+ DSel=0 DScale=2 PME-
03:04.0 Ethernet controller: Broadcom Corporation NetXtreme BCM5704S Gigabit
Ethernet (rev 03)
Subsystem: Broadcom Corporation NetXtreme BCM5704S Gigabit Ethernet
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR+ FastB2B-
Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
Latency: 64 (16000ns min), Cache Line Size 10
Interrupt: pin A routed to IRQ 9
Region 0: Memory at fead0000 (64-bit, non-prefetchable) [size=64K]
Region 2: Memory at feac0000 (64-bit, non-prefetchable) [size=64K]
Capabilities: [40] PCI-X non-bridge device.
Command: DPERE- ERO+ RBC=0 OST=0
Status: Bus=3 Dev=4 Func=0 64bit+ 133MHz+ SCD- USC-, DC=simple,
DMMRBC=2, DMOST=0, DMCRS=1, RSCEM-
Capabilities: [48] Power Management version 2
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
PME(D0-,D1-,D2-,D3hot+,D3cold+)
Status: D0 PME-Enable- DSel=0 DScale=1 PME-
Capabilities: [50] Vital Product Data
Capabilities: [58] Message Signalled Interrupts: 64bit+ Queue=0/3
Enable-
Address: dfa422e80ca5c568 Data: 3204
03:04.1 Ethernet controller: Broadcom Corporation NetXtreme BCM5704S Gigabit
Ethernet (rev 03)
Subsystem: Broadcom Corporation NetXtreme BCM5704S Gigabit Ethernet
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR+ FastB2B-
Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
Latency: 64 (16000ns min), Cache Line Size 10
Interrupt: pin B routed to IRQ 5
Region 0: Memory at feaf0000 (64-bit, non-prefetchable) [size=64K]
Region 2: Memory at feae0000 (64-bit, non-prefetchable) [size=64K]
Capabilities: [40] PCI-X non-bridge device.
Command: DPERE- ERO+ RBC=0 OST=0
Status: Bus=3 Dev=4 Func=1 64bit+ 133MHz+ SCD- USC-, DC=simple,
DMMRBC=2, DMOST=0, DMCRS=1, RSCEM-
Capabilities: [48] Power Management version 2
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
PME(D0-,D1-,D2-,D3hot+,D3cold+)
Status: D0 PME-Enable- DSel=0 DScale=1 PME-
Capabilities: [50] Vital Product Data
Capabilities: [58] Message Signalled Interrupts: 64bit+ Queue=0/3
Enable-
Address: 67b8a6dfdfacc548 Data: 77bf
LinuxBIOS-1.1.8_s2880_Fallback Wed May 10 17:57:29 CST 2006 starting... 00 cache_as_ram_auto.c setting up resource map.... 0000c144 <-00000000 0000c14c <-00000001 0000c154 <-00000002 0000c15c <-00000003 0000c164 <-00000004 0000c16c <-00000005 0000c174 <-00000006 0000c17c <-00000007 0000c140 <-00000000 0000c148 <-00000000 0000c150 <-00000000 0000c158 <-00000000 0000c160 <-00000000 0000c168 <-00000000 0000c170 <-00000000 0000c178 <-00000000 0000c184 <-00000000 0000c18c <-00000000 0000c194 <-00000000 0000c19c <-00000000 0000c1a4 <-00000000 0000c1ac <-00000000 0000c1b4 <-00000000 0000c1bc <-00ffff00 0000c180 <-00000000 0000c188 <-00000000 0000c190 <-00000000 0000c198 <-00000000 0000c1a0 <-00000000 0000c1a8 <-00000000 0000c1b0 <-00000000 0000c1b8 <-00fc0003 0000c1c4 <-01fff000 0000c1cc <-00000000 0000c1d4 <-
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