Ronald G Minnich <[EMAIL PROTECTED]> writes:
> On Thu, 8 Mar 2001 [EMAIL PROTECTED] wrote:
>
> > Wouldn't memset(0, 0, size_of_memory) be faster since you skip reading
> > memory?
>
> no, that's the key thing that Eric pointed out. You don't really skip
> reading it, I don't think, since the cache hardware will read the cache
> line before you write to it. Getting around that is probably tough, since
> the cache hardware should do that.
Actually the the cache hardware normally does skip this, but
occasionally it's slow path get's triggered, so you can't count on it.
However if you hack the mtrrs so that the memory is mapped
write-combining you can write at full speed. And back to back writes
are faster than reading with SDRAM, (It's the way the protocol is
implemented). So you should be able to get about 600MB/s with PC100
SDRAM.
However if we can detect a reset it is probably o.k. to skip the RAM
initialization altogether, (because we have done it already).
The hard question is how do we tell things that only work most of
the time from techniques that work all of the time.
Eric
