Jeremy Jackson <[EMAIL PROTECTED]> writes:
> from the Alpha Architecture Handbook v4:
>
> Description: The WH64 instruction provides a hint that the current contents of
> the aligned 64-byte block containing the addressed byte will *never be read
> again but will be overwritten in the near future*.
> Perhaps intel PIII's SSE has similar functionality?
Possibly.
The following SROM code sequence:
SweepMemory:
mb
subq r19, 0x40, r19 /* Decrement pointer */
whint r18
mb
stq r31, 0x00(r18) /* Store same Quadword */
stq r31, 0x08(r18) /* Store same Quadword */
stq r31, 0x10(r18) /* Store same Quadword */
stq r31, 0x18(r18) /* Store same Quadword */
stq r31, 0x20(r18) /* Store same Quadword */
stq r31, 0x28(r18) /* Store same Quadword */
stq r31, 0x30(r18) /* Store same Quadword */
stq r31, 0x38(r18) /* Store same Quadword */
mb
ecb r18
addq r18, 0x40, r18 /* increment pointer */
mb // lets stop spec stores
Does not work reliably to suppress all cache reads.
It supresses most cache reads however. On x86 I expect the same kind
of behavior from hint instructions. Only in a mode with caching disabled
can you reliably count on not getting a read-modify-write cycle. And even
then you need to meet some criteria so you have a full block to write.
Use Write-Combining with x86 mtrrs to do this.
If you are being clever and not disabling cache you must instrument your
memory write path and see the code fail sometimes. I assisted with a project
that attempted to use the alpha memory bus for general purpose I/O. It failed
because the alpha cannot disable caching on RAM.
The processor occasionally doesn't honor your hints and you are toast.
RAM seems to initialize to 0 on power up so no one notice problems however.
Eric
