on 4GB *PLUS* systems? could the memory hole at 15-16 MB on some chipsets be used to avoid reducing memory size?
----- Original Message ----- From: "Eric W. Biederman" <[EMAIL PROTECTED]> To: "Ronald G Minnich" <[EMAIL PROTECTED]> Cc: <[EMAIL PROTECTED]> Sent: Wednesday, January 09, 2002 12:59 PM Subject: Re: pci setup bug. > Ronald G Minnich <[EMAIL PROTECTED]> writes: > > > Fooey. I thought all these were fixed. > > > > LinuxBIOS pci setup is not setting up BARs totally according to PCI spec. > > We are not aligning them correctly. Amazingly enough today is the first > > day this bug caused us any trouble ... symptom was in etherboot, a tulip > > card would not respond to I/O addresses as linuxbios configured BAR 1 to > > 0x1030, it is a 64-byte space and the address needs to be 64-byte > > aligned. > > > > I'll try to get the fix in today. > > Interesting. Given that this is the second fix we have put in recently > to the pci code, counting the nested pci bridge fix, and vga card fix > as one fix. > > It looks like we have reached another level of maturity. We just > got a whole flock of new bugs discovered, and fixed :) > > The truly interesting pci setup trick is when the amount of memory we > setup needs to be reduced to allow room for pci memory regions. This > happens on 4GB+ boxes. > > Eric >
