On Thursday 10 January 2002 09:05, Christopher Stutts wrote: > While porting to my non-PC 440BX-equipped board, I had to do 3 things: > align the IO, worry about nested bridges, and the 3rd was to force the > PIIX4 function 3 config regs 40h & 90h into the IO list. These weren't > being scanned, but they must be setup. I also see couple non-standard > register addresses in the 815 chipset that would not be enumerated by > default: device/vendor 24408086 bus/dev/func/reg 0/31/0/40h & > 0/31/0/58h.
Thanks for this note. I hope we have as of now fixed the IO alignment and nested bridges, can you check? The PIIX4 problem is that Intel have cleverly put I/O register bases in the chip that are not in the BAR space. I'm not quite sure why they did this. But it means you have to do I/O allocation outside all the PCI I/O allocation. It looks like they continue this tradition with the newer chips. ron
